2018-03-22 01:04:45 +01:00
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/**
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* Marlin 3D Printer Firmware
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2020-02-03 15:00:57 +01:00
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* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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2018-03-22 01:04:45 +01:00
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*
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* Based on Sprinter and grbl.
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2019-06-28 06:57:50 +02:00
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* Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
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2018-03-22 01:04:45 +01:00
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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2020-07-23 05:20:14 +02:00
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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2018-03-22 01:04:45 +01:00
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*
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*/
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#ifdef ARDUINO_ARCH_SAM
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2018-10-03 05:09:41 +02:00
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#include "../../core/macros.h"
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2018-05-20 08:33:21 +02:00
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#include "../../core/serial.h"
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2018-08-21 04:11:12 +02:00
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#include "../shared/backtrace/unwinder.h"
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#include "../shared/backtrace/unwmemaccess.h"
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2018-03-22 01:04:45 +01:00
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2019-06-23 10:43:36 +02:00
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#include <stdarg.h>
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2018-03-22 01:04:45 +01:00
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// Debug monitor that dumps to the Programming port all status when
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// an exception or WDT timeout happens - And then resets the board
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// All the Monitor routines must run with interrupts disabled and
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// under an ISR execution context. That is why we cannot reuse the
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// Serial interrupt routines or any C runtime, as we don't know the
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// state we are when running them
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// A SW memory barrier, to ensure GCC does not overoptimize loops
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2018-05-08 12:10:27 +02:00
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#define sw_barrier() __asm__ volatile("": : :"memory");
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2018-03-22 01:04:45 +01:00
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// (re)initialize UART0 as a monitor output to 250000,n,8,1
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2019-09-17 03:31:08 +02:00
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static void TXBegin() {
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2018-03-22 01:04:45 +01:00
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( UART_IRQn );
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2018-05-16 21:38:17 +02:00
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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2018-03-22 01:04:45 +01:00
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// Disable clock
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pmc_disable_periph_clk( ID_UART );
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// Configure PMC
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pmc_enable_periph_clk( ID_UART );
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// Disable PDC channel
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UART->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
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// Reset and disable receiver and transmitter
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UART->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
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// Configure mode: 8bit, No parity, 1 bit stop
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UART->UART_MR = UART_MR_CHMODE_NORMAL | US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO;
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2018-03-22 07:34:03 +01:00
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// Configure baudrate (asynchronous, no oversampling) to BAUDRATE bauds
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UART->UART_BRGR = (SystemCoreClock / (BAUDRATE << 4));
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2018-03-22 01:04:45 +01:00
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// Enable receiver and transmitter
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UART->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
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}
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// Send character through UART with no interrupts
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static void TX(char c) {
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while (!(UART->UART_SR & UART_SR_TXRDY)) { WDT_Restart(WDT); sw_barrier(); };
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UART->UART_THR = c;
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}
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// Send String through UART
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static void TX(const char* s) {
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2018-04-01 01:48:51 +02:00
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while (*s) TX(*s++);
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2018-03-22 01:04:45 +01:00
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}
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static void TXDigit(uint32_t d) {
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if (d < 10) TX((char)(d+'0'));
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else if (d < 16) TX((char)(d+'A'-10));
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else TX('?');
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}
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// Send Hex number thru UART
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static void TXHex(uint32_t v) {
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TX("0x");
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2018-04-01 01:48:51 +02:00
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for (uint8_t i = 0; i < 8; i++, v <<= 4)
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2018-03-22 01:04:45 +01:00
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TXDigit((v >> 28) & 0xF);
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}
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2018-03-22 07:34:03 +01:00
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// Send Decimal number thru UART
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static void TXDec(uint32_t v) {
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if (!v) {
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TX('0');
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return;
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}
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char nbrs[14];
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char *p = &nbrs[0];
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while (v != 0) {
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*p++ = '0' + (v % 10);
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v /= 10;
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}
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do {
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p--;
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TX(*p);
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} while (p != &nbrs[0]);
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}
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// Dump a backtrace entry
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2018-03-25 05:52:04 +02:00
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static bool UnwReportOut(void* ctx, const UnwReport* bte) {
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2018-03-26 08:42:54 +02:00
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int* p = (int*)ctx;
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2018-03-25 05:52:04 +02:00
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2018-03-26 08:42:54 +02:00
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(*p)++;
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TX('#'); TXDec(*p); TX(" : ");
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TX(bte->name?bte->name:"unknown"); TX('@'); TXHex(bte->function);
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2018-03-25 05:52:04 +02:00
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TX('+'); TXDec(bte->address - bte->function);
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TX(" PC:");TXHex(bte->address); TX('\n');
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return true;
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2018-03-22 07:34:03 +01:00
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}
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2018-04-01 01:48:51 +02:00
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#ifdef UNW_DEBUG
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void UnwPrintf(const char* format, ...) {
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char dest[256];
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va_list argptr;
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va_start(argptr, format);
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vsprintf(dest, format, argptr);
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va_end(argptr);
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TX(&dest[0]);
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}
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2018-03-26 08:42:54 +02:00
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#endif
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2018-03-25 05:52:04 +02:00
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/* Table of function pointers for passing to the unwinder */
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static const UnwindCallbacks UnwCallbacks = {
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UnwReportOut,
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UnwReadW,
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UnwReadH,
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UnwReadB
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2018-11-11 00:51:49 +01:00
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#ifdef UNW_DEBUG
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, UnwPrintf
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2018-04-01 01:48:51 +02:00
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#endif
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2018-03-25 05:52:04 +02:00
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};
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2018-03-22 01:04:45 +01:00
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/**
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* HardFaultHandler_C:
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* This is called from the HardFault_HandlerAsm with a pointer the Fault stack
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* as the parameter. We can then read the values from the stack and place them
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* into local variables for ease of reading.
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* We then read the various Fault Status and Address Registers to help decode
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* cause of the fault.
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* The function ends with a BKPT instruction to force control back into the debugger
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*/
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extern "C"
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2018-03-26 08:42:54 +02:00
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void HardFault_HandlerC(unsigned long *sp, unsigned long lr, unsigned long cause) {
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2018-03-22 01:04:45 +01:00
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static const char* causestr[] = {
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"NMI","Hard","Mem","Bus","Usage","Debug","WDT","RSTC"
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};
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2018-03-26 08:42:54 +02:00
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UnwindFrame btf;
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2018-03-22 01:04:45 +01:00
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// Dump report to the Programming port (interrupts are DISABLED)
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TXBegin();
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TX("\n\n## Software Fault detected ##\n");
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TX("Cause: "); TX(causestr[cause]); TX('\n');
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2018-03-26 08:42:54 +02:00
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TX("R0 : "); TXHex(((unsigned long)sp[0])); TX('\n');
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TX("R1 : "); TXHex(((unsigned long)sp[1])); TX('\n');
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TX("R2 : "); TXHex(((unsigned long)sp[2])); TX('\n');
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TX("R3 : "); TXHex(((unsigned long)sp[3])); TX('\n');
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TX("R12 : "); TXHex(((unsigned long)sp[4])); TX('\n');
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TX("LR : "); TXHex(((unsigned long)sp[5])); TX('\n');
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TX("PC : "); TXHex(((unsigned long)sp[6])); TX('\n');
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TX("PSR : "); TXHex(((unsigned long)sp[7])); TX('\n');
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2018-03-22 01:04:45 +01:00
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// Configurable Fault Status Register
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// Consists of MMSR, BFSR and UFSR
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TX("CFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED28)))); TX('\n');
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// Hard Fault Status Register
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TX("HFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED2C)))); TX('\n');
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// Debug Fault Status Register
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TX("DFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED30)))); TX('\n');
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// Auxiliary Fault Status Register
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TX("AFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED3C)))); TX('\n');
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// Read the Fault Address Registers. These may not contain valid values.
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// Check BFARVALID/MMARVALID to see if they are valid values
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// MemManage Fault Address Register
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TX("MMAR : "); TXHex((*((volatile unsigned long *)(0xE000ED34)))); TX('\n');
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// Bus Fault Address Register
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TX("BFAR : "); TXHex((*((volatile unsigned long *)(0xE000ED38)))); TX('\n');
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2018-03-26 08:42:54 +02:00
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TX("ExcLR: "); TXHex(lr); TX('\n');
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TX("ExcSP: "); TXHex((unsigned long)sp); TX('\n');
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btf.sp = ((unsigned long)sp) + 8*4; // The original stack pointer
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btf.fp = btf.sp;
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btf.lr = ((unsigned long)sp[5]);
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btf.pc = ((unsigned long)sp[6]) | 1; // Force Thumb, as CORTEX only support it
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2018-03-22 07:34:03 +01:00
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// Perform a backtrace
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TX("\nBacktrace:\n\n");
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2018-03-26 08:42:54 +02:00
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int ctr = 0;
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UnwindStart(&btf, &UnwCallbacks, &ctr);
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2018-03-22 07:34:03 +01:00
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2018-03-23 09:22:45 +01:00
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// Disable all NVIC interrupts
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NVIC->ICER[0] = 0xFFFFFFFF;
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NVIC->ICER[1] = 0xFFFFFFFF;
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// Relocate VTOR table to default position
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SCB->VTOR = 0;
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// Disable USB
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otg_disable();
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// Restart watchdog
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WDT_Restart(WDT);
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2018-03-22 01:04:45 +01:00
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// Reset controller
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NVIC_SystemReset();
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2019-02-12 23:25:49 +01:00
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for (;;) WDT_Restart(WDT);
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2018-03-22 01:04:45 +01:00
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}
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2019-09-17 03:31:08 +02:00
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__attribute__((naked)) void NMI_Handler() {
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2018-03-28 20:13:20 +02:00
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__asm__ __volatile__ (
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2018-05-08 12:10:27 +02:00
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".syntax unified" "\n\t"
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A("tst lr, #4")
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A("ite eq")
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A("mrseq r0, msp")
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A("mrsne r0, psp")
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A("mov r1,lr")
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A("mov r2,#0")
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A("b HardFault_HandlerC")
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2018-03-22 01:04:45 +01:00
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);
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}
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2019-09-17 03:31:08 +02:00
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__attribute__((naked)) void HardFault_Handler() {
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2018-03-28 20:13:20 +02:00
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__asm__ __volatile__ (
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2018-05-08 12:10:27 +02:00
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".syntax unified" "\n\t"
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A("tst lr, #4")
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A("ite eq")
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A("mrseq r0, msp")
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A("mrsne r0, psp")
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A("mov r1,lr")
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A("mov r2,#1")
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A("b HardFault_HandlerC")
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2018-03-22 01:04:45 +01:00
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);
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}
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2019-09-17 03:31:08 +02:00
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__attribute__((naked)) void MemManage_Handler() {
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2018-03-28 20:13:20 +02:00
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__asm__ __volatile__ (
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2018-05-08 12:10:27 +02:00
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".syntax unified" "\n\t"
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A("tst lr, #4")
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A("ite eq")
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A("mrseq r0, msp")
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A("mrsne r0, psp")
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A("mov r1,lr")
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A("mov r2,#2")
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A("b HardFault_HandlerC")
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2018-03-22 01:04:45 +01:00
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);
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}
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2019-09-17 03:31:08 +02:00
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__attribute__((naked)) void BusFault_Handler() {
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2018-03-28 20:13:20 +02:00
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__asm__ __volatile__ (
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2018-05-08 12:10:27 +02:00
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".syntax unified" "\n\t"
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A("tst lr, #4")
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A("ite eq")
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A("mrseq r0, msp")
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A("mrsne r0, psp")
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A("mov r1,lr")
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A("mov r2,#3")
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A("b HardFault_HandlerC")
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2018-03-22 01:04:45 +01:00
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);
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}
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2019-09-17 03:31:08 +02:00
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__attribute__((naked)) void UsageFault_Handler() {
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2018-03-28 20:13:20 +02:00
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__asm__ __volatile__ (
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2018-05-08 12:10:27 +02:00
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".syntax unified" "\n\t"
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A("tst lr, #4")
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A("ite eq")
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A("mrseq r0, msp")
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A("mrsne r0, psp")
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A("mov r1,lr")
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A("mov r2,#4")
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A("b HardFault_HandlerC")
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2018-03-22 01:04:45 +01:00
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);
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}
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2019-09-17 03:31:08 +02:00
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__attribute__((naked)) void DebugMon_Handler() {
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2018-03-28 20:13:20 +02:00
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__asm__ __volatile__ (
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2018-05-08 12:10:27 +02:00
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".syntax unified" "\n\t"
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A("tst lr, #4")
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A("ite eq")
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A("mrseq r0, msp")
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A("mrsne r0, psp")
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A("mov r1,lr")
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A("mov r2,#5")
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A("b HardFault_HandlerC")
|
2018-03-22 01:04:45 +01:00
|
|
|
);
|
|
|
|
}
|
|
|
|
|
2018-03-26 08:42:54 +02:00
|
|
|
/* This is NOT an exception, it is an interrupt handler - Nevertheless, the framing is the same */
|
2019-09-17 03:31:08 +02:00
|
|
|
__attribute__((naked)) void WDT_Handler() {
|
2018-03-28 20:13:20 +02:00
|
|
|
__asm__ __volatile__ (
|
2018-05-08 12:10:27 +02:00
|
|
|
".syntax unified" "\n\t"
|
|
|
|
A("tst lr, #4")
|
|
|
|
A("ite eq")
|
|
|
|
A("mrseq r0, msp")
|
|
|
|
A("mrsne r0, psp")
|
|
|
|
A("mov r1,lr")
|
|
|
|
A("mov r2,#6")
|
|
|
|
A("b HardFault_HandlerC")
|
2018-03-22 01:04:45 +01:00
|
|
|
);
|
|
|
|
}
|
|
|
|
|
2019-09-17 03:31:08 +02:00
|
|
|
__attribute__((naked)) void RSTC_Handler() {
|
2018-03-28 20:13:20 +02:00
|
|
|
__asm__ __volatile__ (
|
2018-05-08 12:10:27 +02:00
|
|
|
".syntax unified" "\n\t"
|
|
|
|
A("tst lr, #4")
|
|
|
|
A("ite eq")
|
|
|
|
A("mrseq r0, msp")
|
|
|
|
A("mrsne r0, psp")
|
|
|
|
A("mov r1,lr")
|
|
|
|
A("mov r2,#7")
|
|
|
|
A("b HardFault_HandlerC")
|
2018-03-22 01:04:45 +01:00
|
|
|
);
|
|
|
|
}
|
|
|
|
|
2018-05-20 08:33:21 +02:00
|
|
|
#endif // ARDUINO_ARCH_SAM
|