2017-05-21 16:42:39 +02:00
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/**
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* Marlin 3D Printer Firmware
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2019-02-12 22:06:53 +01:00
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* Copyright (C) 2019 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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2017-05-21 16:42:39 +02:00
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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2018-11-04 09:25:55 +01:00
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#pragma once
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2017-05-21 16:42:39 +02:00
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/**
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* Pin mapping for the 1281 and 2561
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*
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2018-03-20 22:24:50 +01:00
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* Logical Pin: 38 39 40 41 42 43 44 45 16 10 11 12 06 07 08 09 30 31 32 33 34 35 36 37 17 18 19 20 21 22 23 24 00 01 13 05 02 03 14 15 46 47 48 49 50 51 52 53 25 26 27 28 29 04
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* Port: A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 E0 E1 E2 E3 E4 E5 E6 E7 F0 F1 F2 F3 F4 F5 F6 F7 G0 G1 G2 G3 G4 G5
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2017-05-21 16:42:39 +02:00
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*/
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2017-06-18 01:36:10 +02:00
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#include "fastio_AVR.h"
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2017-05-21 16:42:39 +02:00
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// change for your board
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#define DEBUG_LED DIO46
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// UART
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#define RXD DIO0
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#define TXD DIO1
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// SPI
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#define SCK DIO10
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#define MISO DIO12
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#define MOSI DIO11
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#define SS DIO16
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// TWI (I2C)
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#define SCL DIO17
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#define SDA DIO18
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// Timers and PWM
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#define OC0A DIO9
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#define OC0B DIO4
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#define OC1A DIO7
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#define OC1B DIO8
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#define OC2A DIO6
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#define OC3A DIO5
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#define OC3B DIO2
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#define OC3C DIO3
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// Digital I/O
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#define DIO0_PIN PINE0
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#define DIO0_RPORT PINE
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#define DIO0_WPORT PORTE
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#define DIO0_DDR DDRE
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#define DIO0_PWM nullptr
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#define DIO1_PIN PINE1
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#define DIO1_RPORT PINE
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#define DIO1_WPORT PORTE
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#define DIO1_DDR DDRE
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#define DIO1_PWM nullptr
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#define DIO2_PIN PINE4
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#define DIO2_RPORT PINE
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#define DIO2_WPORT PORTE
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#define DIO2_DDR DDRE
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#define DIO2_PWM &OCR3BL
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#define DIO3_PIN PINE5
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#define DIO3_RPORT PINE
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#define DIO3_WPORT PORTE
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#define DIO3_DDR DDRE
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#define DIO3_PWM &OCR3CL
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#define DIO4_PIN PING5
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#define DIO4_RPORT PING
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#define DIO4_WPORT PORTG
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#define DIO4_DDR DDRG
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#define DIO4_PWM &OCR0B
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#define DIO5_PIN PINE3
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#define DIO5_RPORT PINE
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#define DIO5_WPORT PORTE
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#define DIO5_DDR DDRE
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#define DIO5_PWM &OCR3AL
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#define DIO6_PIN PINB4
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#define DIO6_RPORT PINB
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#define DIO6_WPORT PORTB
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#define DIO6_DDR DDRB
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#define DIO6_PWM &OCR2AL
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#define DIO7_PIN PINB5
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#define DIO7_RPORT PINB
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#define DIO7_WPORT PORTB
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#define DIO7_DDR DDRB
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#define DIO7_PWM &OCR1AL
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#define DIO8_PIN PINB6
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#define DIO8_RPORT PINB
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#define DIO8_WPORT PORTB
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#define DIO8_DDR DDRB
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#define DIO8_PWM &OCR1BL
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#define DIO9_PIN PINB7
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#define DIO9_RPORT PINB
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#define DIO9_WPORT PORTB
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#define DIO9_DDR DDRB
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#define DIO9_PWM &OCR0AL
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#define DIO10_PIN PINB1
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#define DIO10_RPORT PINB
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#define DIO10_WPORT PORTB
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#define DIO10_DDR DDRB
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#define DIO10_PWM nullptr
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#define DIO11_PIN PINB2
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#define DIO11_RPORT PINB
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#define DIO11_WPORT PORTB
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#define DIO11_DDR DDRB
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#define DIO11_PWM nullptr
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#define DIO12_PIN PINB3
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#define DIO12_RPORT PINB
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#define DIO12_WPORT PORTB
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#define DIO12_DDR DDRB
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#define DIO12_PWM nullptr
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#define DIO13_PIN PINE2
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#define DIO13_RPORT PINE
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#define DIO13_WPORT PORTE
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#define DIO13_DDR DDRE
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#define DIO13_PWM nullptr
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#define DIO14_PIN PINE6
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#define DIO14_RPORT PINE
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#define DIO14_WPORT PORTE
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#define DIO14_DDR DDRE
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#define DIO14_PWM nullptr
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#define DIO15_PIN PINE7
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#define DIO15_RPORT PINE
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#define DIO15_WPORT PORTE
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#define DIO15_DDR DDRE
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#define DIO15_PWM nullptr
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#define DIO16_PIN PINB0
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#define DIO16_RPORT PINB
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#define DIO16_WPORT PORTB
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#define DIO16_DDR DDRB
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#define DIO16_PWM nullptr
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#define DIO17_PIN PIND0
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#define DIO17_RPORT PIND
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#define DIO17_WPORT PORTD
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#define DIO17_DDR DDRD
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#define DIO17_PWM nullptr
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#define DIO18_PIN PIND1
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#define DIO18_RPORT PIND
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#define DIO18_WPORT PORTD
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#define DIO18_DDR DDRD
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#define DIO18_PWM nullptr
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#define DIO19_PIN PIND2
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#define DIO19_RPORT PIND
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#define DIO19_WPORT PORTD
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#define DIO19_DDR DDRD
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#define DIO19_PWM nullptr
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#define DIO20_PIN PIND3
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#define DIO20_RPORT PIND
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#define DIO20_WPORT PORTD
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#define DIO20_DDR DDRD
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#define DIO20_PWM nullptr
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#define DIO21_PIN PIND4
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#define DIO21_RPORT PIND
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#define DIO21_WPORT PORTD
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#define DIO21_DDR DDRD
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#define DIO21_PWM nullptr
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#define DIO22_PIN PIND5
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#define DIO22_RPORT PIND
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#define DIO22_WPORT PORTD
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#define DIO22_DDR DDRD
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#define DIO22_PWM nullptr
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#define DIO23_PIN PIND6
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#define DIO23_RPORT PIND
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#define DIO23_WPORT PORTD
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#define DIO23_DDR DDRD
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#define DIO23_PWM nullptr
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#define DIO24_PIN PIND7
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#define DIO24_RPORT PIND
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#define DIO24_WPORT PORTD
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#define DIO24_DDR DDRD
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#define DIO24_PWM nullptr
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#define DIO25_PIN PING0
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#define DIO25_RPORT PING
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#define DIO25_WPORT PORTG
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#define DIO25_DDR DDRG
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#define DIO25_PWM nullptr
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#define DIO26_PIN PING1
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#define DIO26_RPORT PING
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#define DIO26_WPORT PORTG
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#define DIO26_DDR DDRG
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#define DIO26_PWM nullptr
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#define DIO27_PIN PING2
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#define DIO27_RPORT PING
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#define DIO27_WPORT PORTG
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#define DIO27_DDR DDRG
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#define DIO27_PWM nullptr
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#define DIO28_PIN PING3
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#define DIO28_RPORT PING
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#define DIO28_WPORT PORTG
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#define DIO28_DDR DDRG
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#define DIO28_PWM nullptr
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#define DIO29_PIN PING4
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#define DIO29_RPORT PING
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#define DIO29_WPORT PORTG
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#define DIO29_DDR DDRG
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#define DIO29_PWM nullptr
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#define DIO30_PIN PINC0
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#define DIO30_RPORT PINC
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#define DIO30_WPORT PORTC
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#define DIO30_DDR DDRC
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#define DIO30_PWM nullptr
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#define DIO31_PIN PINC1
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#define DIO31_RPORT PINC
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#define DIO31_WPORT PORTC
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#define DIO31_DDR DDRC
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#define DIO31_PWM nullptr
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#define DIO32_PIN PINC2
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#define DIO32_RPORT PINC
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#define DIO32_WPORT PORTC
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#define DIO32_DDR DDRC
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#define DIO32_PWM nullptr
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#define DIO33_PIN PINC3
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#define DIO33_RPORT PINC
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#define DIO33_WPORT PORTC
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#define DIO33_DDR DDRC
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#define DIO33_PWM nullptr
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#define DIO34_PIN PINC4
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#define DIO34_RPORT PINC
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#define DIO34_WPORT PORTC
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#define DIO34_DDR DDRC
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#define DIO34_PWM nullptr
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#define DIO35_PIN PINC5
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#define DIO35_RPORT PINC
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#define DIO35_WPORT PORTC
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#define DIO35_DDR DDRC
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#define DIO35_PWM nullptr
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#define DIO36_PIN PINC6
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#define DIO36_RPORT PINC
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#define DIO36_WPORT PORTC
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#define DIO36_DDR DDRC
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#define DIO36_PWM nullptr
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#define DIO37_PIN PINC7
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#define DIO37_RPORT PINC
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#define DIO37_WPORT PORTC
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#define DIO37_DDR DDRC
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#define DIO37_PWM nullptr
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#define DIO38_PIN PINA0
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#define DIO38_RPORT PINA
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#define DIO38_WPORT PORTA
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#define DIO38_DDR DDRA
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#define DIO38_PWM nullptr
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#define DIO39_PIN PINA1
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#define DIO39_RPORT PINA
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#define DIO39_WPORT PORTA
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#define DIO39_DDR DDRA
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#define DIO39_PWM nullptr
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#define DIO40_PIN PINA2
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#define DIO40_RPORT PINA
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#define DIO40_WPORT PORTA
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#define DIO40_DDR DDRA
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#define DIO40_PWM nullptr
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#define DIO41_PIN PINA3
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#define DIO41_RPORT PINA
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#define DIO41_WPORT PORTA
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#define DIO41_DDR DDRA
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#define DIO41_PWM nullptr
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#define DIO42_PIN PINA4
|
|
|
|
#define DIO42_RPORT PINA
|
|
|
|
#define DIO42_WPORT PORTA
|
|
|
|
#define DIO42_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO42_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO43_PIN PINA5
|
|
|
|
#define DIO43_RPORT PINA
|
|
|
|
#define DIO43_WPORT PORTA
|
|
|
|
#define DIO43_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO43_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO44_PIN PINA6
|
|
|
|
#define DIO44_RPORT PINA
|
|
|
|
#define DIO44_WPORT PORTA
|
|
|
|
#define DIO44_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO44_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO45_PIN PINA7
|
|
|
|
#define DIO45_RPORT PINA
|
|
|
|
#define DIO45_WPORT PORTA
|
|
|
|
#define DIO45_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO45_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO46_PIN PINF0
|
|
|
|
#define DIO46_RPORT PINF
|
|
|
|
#define DIO46_WPORT PORTF
|
|
|
|
#define DIO46_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO46_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO47_PIN PINF1
|
|
|
|
#define DIO47_RPORT PINF
|
|
|
|
#define DIO47_WPORT PORTF
|
|
|
|
#define DIO47_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO47_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO48_PIN PINF2
|
|
|
|
#define DIO48_RPORT PINF
|
|
|
|
#define DIO48_WPORT PORTF
|
|
|
|
#define DIO48_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO48_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO49_PIN PINF3
|
|
|
|
#define DIO49_RPORT PINF
|
|
|
|
#define DIO49_WPORT PORTF
|
|
|
|
#define DIO49_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO49_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO50_PIN PINF4
|
|
|
|
#define DIO50_RPORT PINF
|
|
|
|
#define DIO50_WPORT PORTF
|
|
|
|
#define DIO50_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO50_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO51_PIN PINF5
|
|
|
|
#define DIO51_RPORT PINF
|
|
|
|
#define DIO51_WPORT PORTF
|
|
|
|
#define DIO51_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO51_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO52_PIN PINF6
|
|
|
|
#define DIO52_RPORT PINF
|
|
|
|
#define DIO52_WPORT PORTF
|
|
|
|
#define DIO52_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO52_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#define DIO53_PIN PINF7
|
|
|
|
#define DIO53_RPORT PINF
|
|
|
|
#define DIO53_WPORT PORTF
|
|
|
|
#define DIO53_DDR DDRF
|
2019-05-09 18:45:55 +02:00
|
|
|
#define DIO53_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#undef PA0
|
|
|
|
#define PA0_PIN PINA0
|
|
|
|
#define PA0_RPORT PINA
|
|
|
|
#define PA0_WPORT PORTA
|
|
|
|
#define PA0_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA1
|
|
|
|
#define PA1_PIN PINA1
|
|
|
|
#define PA1_RPORT PINA
|
|
|
|
#define PA1_WPORT PORTA
|
|
|
|
#define PA1_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA2
|
|
|
|
#define PA2_PIN PINA2
|
|
|
|
#define PA2_RPORT PINA
|
|
|
|
#define PA2_WPORT PORTA
|
|
|
|
#define PA2_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA3
|
|
|
|
#define PA3_PIN PINA3
|
|
|
|
#define PA3_RPORT PINA
|
|
|
|
#define PA3_WPORT PORTA
|
|
|
|
#define PA3_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA3_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA4
|
|
|
|
#define PA4_PIN PINA4
|
|
|
|
#define PA4_RPORT PINA
|
|
|
|
#define PA4_WPORT PORTA
|
|
|
|
#define PA4_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA4_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA5
|
|
|
|
#define PA5_PIN PINA5
|
|
|
|
#define PA5_RPORT PINA
|
|
|
|
#define PA5_WPORT PORTA
|
|
|
|
#define PA5_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA5_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA6
|
|
|
|
#define PA6_PIN PINA6
|
|
|
|
#define PA6_RPORT PINA
|
|
|
|
#define PA6_WPORT PORTA
|
|
|
|
#define PA6_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA6_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PA7
|
|
|
|
#define PA7_PIN PINA7
|
|
|
|
#define PA7_RPORT PINA
|
|
|
|
#define PA7_WPORT PORTA
|
|
|
|
#define PA7_DDR DDRA
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PA7_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#undef PB0
|
|
|
|
#define PB0_PIN PINB0
|
|
|
|
#define PB0_RPORT PINB
|
|
|
|
#define PB0_WPORT PORTB
|
|
|
|
#define PB0_DDR DDRB
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PB0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PB1
|
|
|
|
#define PB1_PIN PINB1
|
|
|
|
#define PB1_RPORT PINB
|
|
|
|
#define PB1_WPORT PORTB
|
|
|
|
#define PB1_DDR DDRB
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PB1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PB2
|
|
|
|
#define PB2_PIN PINB2
|
|
|
|
#define PB2_RPORT PINB
|
|
|
|
#define PB2_WPORT PORTB
|
|
|
|
#define PB2_DDR DDRB
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PB2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PB3
|
|
|
|
#define PB3_PIN PINB3
|
|
|
|
#define PB3_RPORT PINB
|
|
|
|
#define PB3_WPORT PORTB
|
|
|
|
#define PB3_DDR DDRB
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PB3_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PB4
|
|
|
|
#define PB4_PIN PINB4
|
|
|
|
#define PB4_RPORT PINB
|
|
|
|
#define PB4_WPORT PORTB
|
|
|
|
#define PB4_DDR DDRB
|
|
|
|
#define PB4_PWM &OCR2A
|
|
|
|
#undef PB5
|
|
|
|
#define PB5_PIN PINB5
|
|
|
|
#define PB5_RPORT PINB
|
|
|
|
#define PB5_WPORT PORTB
|
|
|
|
#define PB5_DDR DDRB
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PB5_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PB6
|
|
|
|
#define PB6_PIN PINB6
|
|
|
|
#define PB6_RPORT PINB
|
|
|
|
#define PB6_WPORT PORTB
|
|
|
|
#define PB6_DDR DDRB
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PB6_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PB7
|
|
|
|
#define PB7_PIN PINB7
|
|
|
|
#define PB7_RPORT PINB
|
|
|
|
#define PB7_WPORT PORTB
|
|
|
|
#define PB7_DDR DDRB
|
|
|
|
#define PB7_PWM &OCR0A
|
|
|
|
|
|
|
|
#undef PC0
|
|
|
|
#define PC0_PIN PINC0
|
|
|
|
#define PC0_RPORT PINC
|
|
|
|
#define PC0_WPORT PORTC
|
|
|
|
#define PC0_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC1
|
|
|
|
#define PC1_PIN PINC1
|
|
|
|
#define PC1_RPORT PINC
|
|
|
|
#define PC1_WPORT PORTC
|
|
|
|
#define PC1_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC2
|
|
|
|
#define PC2_PIN PINC2
|
|
|
|
#define PC2_RPORT PINC
|
|
|
|
#define PC2_WPORT PORTC
|
|
|
|
#define PC2_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC3
|
|
|
|
#define PC3_PIN PINC3
|
|
|
|
#define PC3_RPORT PINC
|
|
|
|
#define PC3_WPORT PORTC
|
|
|
|
#define PC3_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC3_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC4
|
|
|
|
#define PC4_PIN PINC4
|
|
|
|
#define PC4_RPORT PINC
|
|
|
|
#define PC4_WPORT PORTC
|
|
|
|
#define PC4_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC4_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC5
|
|
|
|
#define PC5_PIN PINC5
|
|
|
|
#define PC5_RPORT PINC
|
|
|
|
#define PC5_WPORT PORTC
|
|
|
|
#define PC5_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC5_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC6
|
|
|
|
#define PC6_PIN PINC6
|
|
|
|
#define PC6_RPORT PINC
|
|
|
|
#define PC6_WPORT PORTC
|
|
|
|
#define PC6_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC6_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PC7
|
|
|
|
#define PC7_PIN PINC7
|
|
|
|
#define PC7_RPORT PINC
|
|
|
|
#define PC7_WPORT PORTC
|
|
|
|
#define PC7_DDR DDRC
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PC7_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#undef PD0
|
|
|
|
#define PD0_PIN PIND0
|
|
|
|
#define PD0_RPORT PIND
|
|
|
|
#define PD0_WPORT PORTD
|
|
|
|
#define PD0_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD1
|
|
|
|
#define PD1_PIN PIND1
|
|
|
|
#define PD1_RPORT PIND
|
|
|
|
#define PD1_WPORT PORTD
|
|
|
|
#define PD1_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD2
|
|
|
|
#define PD2_PIN PIND2
|
|
|
|
#define PD2_RPORT PIND
|
|
|
|
#define PD2_WPORT PORTD
|
|
|
|
#define PD2_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD3
|
|
|
|
#define PD3_PIN PIND3
|
|
|
|
#define PD3_RPORT PIND
|
|
|
|
#define PD3_WPORT PORTD
|
|
|
|
#define PD3_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD3_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD4
|
|
|
|
#define PD4_PIN PIND4
|
|
|
|
#define PD4_RPORT PIND
|
|
|
|
#define PD4_WPORT PORTD
|
|
|
|
#define PD4_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD4_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD5
|
|
|
|
#define PD5_PIN PIND5
|
|
|
|
#define PD5_RPORT PIND
|
|
|
|
#define PD5_WPORT PORTD
|
|
|
|
#define PD5_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD5_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD6
|
|
|
|
#define PD6_PIN PIND6
|
|
|
|
#define PD6_RPORT PIND
|
|
|
|
#define PD6_WPORT PORTD
|
|
|
|
#define PD6_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD6_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PD7
|
|
|
|
#define PD7_PIN PIND7
|
|
|
|
#define PD7_RPORT PIND
|
|
|
|
#define PD7_WPORT PORTD
|
|
|
|
#define PD7_DDR DDRD
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PD7_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
|
|
|
|
#undef PE0
|
|
|
|
#define PE0_PIN PINE0
|
|
|
|
#define PE0_RPORT PINE
|
|
|
|
#define PE0_WPORT PORTE
|
|
|
|
#define PE0_DDR DDRE
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PE0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PE1
|
|
|
|
#define PE1_PIN PINE1
|
|
|
|
#define PE1_RPORT PINE
|
|
|
|
#define PE1_WPORT PORTE
|
|
|
|
#define PE1_DDR DDRE
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PE1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PE2
|
|
|
|
#define PE2_PIN PINE2
|
|
|
|
#define PE2_RPORT PINE
|
|
|
|
#define PE2_WPORT PORTE
|
|
|
|
#define PE2_DDR DDRE
|
2019-05-09 18:45:55 +02:00
|
|
|
#define PE2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
|
|
|
#undef PE3
|
|
|
|
#define PE3_PIN PINE3
|
|
|
|
#define PE3_RPORT PINE
|
|
|
|
#define PE3_WPORT PORTE
|
|
|
|
#define PE3_DDR DDRE
|
|
|
|
#define PE3_PWM &OCR3AL
|
|
|
|
#undef PE4
|
|
|
|
#define PE4_PIN PINE4
|
|
|
|
#define PE4_RPORT PINE
|
|
|
|
#define PE4_WPORT PORTE
|
|
|
|
#define PE4_DDR DDRE
|
|
|
|
#define PE4_PWM &OCR3BL
|
|
|
|
#undef PE5
|
|
|
|
#define PE5_PIN PINE5
|
|
|
|
#define PE5_RPORT PINE
|
|
|
|
#define PE5_WPORT PORTE
|
|
|
|
#define PE5_DDR DDRE
|
|
|
|
#define PE5_PWM &OCR3CL
|
|
|
|
#undef PE6
|
|
|
|
#define PE6_PIN PINE6
|
|
|
|
#define PE6_RPORT PINE
|
|
|
|
#define PE6_WPORT PORTE
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#define PE6_DDR DDRE
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2019-05-09 18:45:55 +02:00
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#define PE6_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PE7
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#define PE7_PIN PINE7
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#define PE7_RPORT PINE
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#define PE7_WPORT PORTE
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#define PE7_DDR DDRE
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2019-05-09 18:45:55 +02:00
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#define PE7_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF0
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#define PF0_PIN PINF0
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#define PF0_RPORT PINF
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#define PF0_WPORT PORTF
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#define PF0_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF0_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF1
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#define PF1_PIN PINF1
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#define PF1_RPORT PINF
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#define PF1_WPORT PORTF
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#define PF1_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF1_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF2
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#define PF2_PIN PINF2
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#define PF2_RPORT PINF
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#define PF2_WPORT PORTF
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#define PF2_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF2_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF3
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#define PF3_PIN PINF3
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#define PF3_RPORT PINF
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#define PF3_WPORT PORTF
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#define PF3_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF3_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF4
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#define PF4_PIN PINF4
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#define PF4_RPORT PINF
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#define PF4_WPORT PORTF
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#define PF4_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF4_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF5
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#define PF5_PIN PINF5
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#define PF5_RPORT PINF
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#define PF5_WPORT PORTF
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#define PF5_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF5_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF6
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#define PF6_PIN PINF6
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#define PF6_RPORT PINF
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#define PF6_WPORT PORTF
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#define PF6_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF6_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PF7
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#define PF7_PIN PINF7
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#define PF7_RPORT PINF
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#define PF7_WPORT PORTF
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#define PF7_DDR DDRF
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2019-05-09 18:45:55 +02:00
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#define PF7_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PG0
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#define PG0_PIN PING0
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#define PG0_RPORT PING
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#define PG0_WPORT PORTG
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#define PG0_DDR DDRG
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2019-05-09 18:45:55 +02:00
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#define PG0_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PG1
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#define PG1_PIN PING1
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#define PG1_RPORT PING
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#define PG1_WPORT PORTG
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#define PG1_DDR DDRG
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2019-05-09 18:45:55 +02:00
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#define PG1_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PG2
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#define PG2_PIN PING2
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#define PG2_RPORT PING
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#define PG2_WPORT PORTG
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#define PG2_DDR DDRG
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2019-05-09 18:45:55 +02:00
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#define PG2_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PG3
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#define PG3_PIN PING3
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#define PG3_RPORT PING
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#define PG3_WPORT PORTG
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#define PG3_DDR DDRG
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2019-05-09 18:45:55 +02:00
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#define PG3_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PG4
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#define PG4_PIN PING4
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#define PG4_RPORT PING
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#define PG4_WPORT PORTG
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#define PG4_DDR DDRG
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2019-05-09 18:45:55 +02:00
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#define PG4_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PG5
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#define PG5_PIN PING5
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#define PG5_RPORT PING
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#define PG5_WPORT PORTG
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#define PG5_DDR DDRG
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#define PG5_PWM &OCR0B
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