2017-05-21 16:42:39 +02:00
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/**
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* Marlin 3D Printer Firmware
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2019-02-12 22:06:53 +01:00
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* Copyright (C) 2019 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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2017-05-21 16:42:39 +02:00
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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2018-11-04 09:25:55 +01:00
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#pragma once
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2017-05-21 16:42:39 +02:00
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/**
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* Pin mapping for the 644, 644p, 644pa, and 1284p
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*
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2018-03-20 22:24:50 +01:00
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* Logical Pin: 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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* Port: B0 B1 B2 B3 B4 B5 B6 B7 D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 A7 A6 A5 A4 A3 A2 A1 A0
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2017-05-21 16:42:39 +02:00
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*/
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2018-03-01 10:07:39 +01:00
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/** ATMega644
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*
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* +---\/---+
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* (D 0) PB0 1| |40 PA0 (AI 0 / D31)
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* (D 1) PB1 2| |39 PA1 (AI 1 / D30)
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* INT2 (D 2) PB2 3| |38 PA2 (AI 2 / D29)
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* PWM (D 3) PB3 4| |37 PA3 (AI 3 / D28)
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* PWM (D 4) PB4 5| |36 PA4 (AI 4 / D27)
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* MOSI (D 5) PB5 6| |35 PA5 (AI 5 / D26)
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* MISO (D 6) PB6 7| |34 PA6 (AI 6 / D25)
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* SCK (D 7) PB7 8| |33 PA7 (AI 7 / D24)
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* RST 9| |32 AREF
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* VCC 10| |31 GND
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* GND 11| |30 AVCC
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* XTAL2 12| |29 PC7 (D 23)
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* XTAL1 13| |28 PC6 (D 22)
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* RX0 (D 8) PD0 14| |27 PC5 (D 21) TDI
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* TX0 (D 9) PD1 15| |26 PC4 (D 20) TDO
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* INT0 RX1 (D 10) PD2 16| |25 PC3 (D 19) TMS
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* INT1 TX1 (D 11) PD3 17| |24 PC2 (D 18) TCK
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* PWM (D 12) PD4 18| |23 PC1 (D 17) SDA
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* PWM (D 13) PD5 19| |22 PC0 (D 16) SCL
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* PWM (D 14) PD6 20| |21 PD7 (D 15) PWM
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* +--------+
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*/
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2017-06-18 01:36:10 +02:00
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#include "fastio_AVR.h"
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2017-05-21 16:42:39 +02:00
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#define DEBUG_LED DIO0
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// UART
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#define RXD DIO8
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#define TXD DIO9
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#define RXD0 DIO8
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#define TXD0 DIO9
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#define RXD1 DIO10
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#define TXD1 DIO11
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// SPI
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#define SCK DIO7
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#define MISO DIO6
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#define MOSI DIO5
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#define SS DIO4
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// TWI (I2C)
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#define SCL DIO16
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#define SDA DIO17
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// Timers and PWM
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#define OC0A DIO3
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#define OC0B DIO4
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#define OC1A DIO13
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#define OC1B DIO12
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#define OC2A DIO15
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#define OC2B DIO14
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// Digital I/O
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#define DIO0_PIN PINB0
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#define DIO0_RPORT PINB
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#define DIO0_WPORT PORTB
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#define DIO0_DDR DDRB
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#define DIO0_PWM nullptr
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#define DIO1_PIN PINB1
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#define DIO1_RPORT PINB
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#define DIO1_WPORT PORTB
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#define DIO1_DDR DDRB
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#define DIO1_PWM nullptr
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#define DIO2_PIN PINB2
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#define DIO2_RPORT PINB
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#define DIO2_WPORT PORTB
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#define DIO2_DDR DDRB
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#define DIO2_PWM nullptr
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#define DIO3_PIN PINB3
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#define DIO3_RPORT PINB
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#define DIO3_WPORT PORTB
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#define DIO3_DDR DDRB
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#define DIO3_PWM &OCR0A
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#define DIO4_PIN PINB4
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#define DIO4_RPORT PINB
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#define DIO4_WPORT PORTB
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#define DIO4_DDR DDRB
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#define DIO4_PWM &OCR0B
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#define DIO5_PIN PINB5
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#define DIO5_RPORT PINB
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#define DIO5_WPORT PORTB
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#define DIO5_DDR DDRB
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#define DIO5_PWM nullptr
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#define DIO6_PIN PINB6
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#define DIO6_RPORT PINB
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#define DIO6_WPORT PORTB
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#define DIO6_DDR DDRB
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#define DIO6_PWM nullptr
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#define DIO7_PIN PINB7
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#define DIO7_RPORT PINB
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#define DIO7_WPORT PORTB
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#define DIO7_DDR DDRB
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#define DIO7_PWM nullptr
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#define DIO8_PIN PIND0
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#define DIO8_RPORT PIND
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#define DIO8_WPORT PORTD
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#define DIO8_DDR DDRD
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#define DIO8_PWM nullptr
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#define DIO9_PIN PIND1
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#define DIO9_RPORT PIND
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#define DIO9_WPORT PORTD
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#define DIO9_DDR DDRD
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#define DIO9_PWM nullptr
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#define DIO10_PIN PIND2
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#define DIO10_RPORT PIND
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#define DIO10_WPORT PORTD
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#define DIO10_DDR DDRD
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#define DIO10_PWM nullptr
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#define DIO11_PIN PIND3
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#define DIO11_RPORT PIND
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#define DIO11_WPORT PORTD
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#define DIO11_DDR DDRD
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#define DIO11_PWM nullptr
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#define DIO12_PIN PIND4
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#define DIO12_RPORT PIND
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#define DIO12_WPORT PORTD
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#define DIO12_DDR DDRD
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#define DIO12_PWM &OCR1B
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#define DIO13_PIN PIND5
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#define DIO13_RPORT PIND
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#define DIO13_WPORT PORTD
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#define DIO13_DDR DDRD
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#define DIO13_PWM &OCR1A
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#define DIO14_PIN PIND6
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#define DIO14_RPORT PIND
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#define DIO14_WPORT PORTD
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#define DIO14_DDR DDRD
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#define DIO14_PWM &OCR2B
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#define DIO15_PIN PIND7
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#define DIO15_RPORT PIND
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#define DIO15_WPORT PORTD
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#define DIO15_DDR DDRD
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#define DIO15_PWM &OCR2A
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#define DIO16_PIN PINC0
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#define DIO16_RPORT PINC
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#define DIO16_WPORT PORTC
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#define DIO16_DDR DDRC
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#define DIO16_PWM nullptr
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#define DIO17_PIN PINC1
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#define DIO17_RPORT PINC
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#define DIO17_WPORT PORTC
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#define DIO17_DDR DDRC
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#define DIO17_PWM nullptr
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#define DIO18_PIN PINC2
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#define DIO18_RPORT PINC
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#define DIO18_WPORT PORTC
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#define DIO18_DDR DDRC
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#define DIO18_PWM nullptr
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#define DIO19_PIN PINC3
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#define DIO19_RPORT PINC
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#define DIO19_WPORT PORTC
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#define DIO19_DDR DDRC
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#define DIO19_PWM nullptr
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#define DIO20_PIN PINC4
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#define DIO20_RPORT PINC
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#define DIO20_WPORT PORTC
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#define DIO20_DDR DDRC
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#define DIO20_PWM nullptr
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#define DIO21_PIN PINC5
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#define DIO21_RPORT PINC
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#define DIO21_WPORT PORTC
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#define DIO21_DDR DDRC
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#define DIO21_PWM nullptr
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#define DIO22_PIN PINC6
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#define DIO22_RPORT PINC
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#define DIO22_WPORT PORTC
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#define DIO22_DDR DDRC
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#define DIO22_PWM nullptr
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#define DIO23_PIN PINC7
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#define DIO23_RPORT PINC
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#define DIO23_WPORT PORTC
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#define DIO23_DDR DDRC
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#define DIO23_PWM nullptr
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#define DIO24_PIN PINA7
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#define DIO24_RPORT PINA
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#define DIO24_WPORT PORTA
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#define DIO24_DDR DDRA
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#define DIO24_PWM nullptr
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#define DIO25_PIN PINA6
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#define DIO25_RPORT PINA
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#define DIO25_WPORT PORTA
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#define DIO25_DDR DDRA
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#define DIO25_PWM nullptr
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#define DIO26_PIN PINA5
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#define DIO26_RPORT PINA
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#define DIO26_WPORT PORTA
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#define DIO26_DDR DDRA
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#define DIO26_PWM nullptr
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#define DIO27_PIN PINA4
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#define DIO27_RPORT PINA
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#define DIO27_WPORT PORTA
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#define DIO27_DDR DDRA
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#define DIO27_PWM nullptr
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#define DIO28_PIN PINA3
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#define DIO28_RPORT PINA
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#define DIO28_WPORT PORTA
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#define DIO28_DDR DDRA
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#define DIO28_PWM nullptr
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#define DIO29_PIN PINA2
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#define DIO29_RPORT PINA
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#define DIO29_WPORT PORTA
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#define DIO29_DDR DDRA
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#define DIO29_PWM nullptr
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#define DIO30_PIN PINA1
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#define DIO30_RPORT PINA
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#define DIO30_WPORT PORTA
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#define DIO30_DDR DDRA
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#define DIO30_PWM nullptr
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#define DIO31_PIN PINA0
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#define DIO31_RPORT PINA
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#define DIO31_WPORT PORTA
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#define DIO31_DDR DDRA
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#define DIO31_PWM nullptr
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#define AIO0_PIN PINA0
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#define AIO0_RPORT PINA
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#define AIO0_WPORT PORTA
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#define AIO0_DDR DDRA
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#define AIO0_PWM nullptr
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#define AIO1_PIN PINA1
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#define AIO1_RPORT PINA
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#define AIO1_WPORT PORTA
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#define AIO1_DDR DDRA
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#define AIO1_PWM nullptr
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#define AIO2_PIN PINA2
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#define AIO2_RPORT PINA
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#define AIO2_WPORT PORTA
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#define AIO2_DDR DDRA
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#define AIO2_PWM nullptr
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#define AIO3_PIN PINA3
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#define AIO3_RPORT PINA
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#define AIO3_WPORT PORTA
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#define AIO3_DDR DDRA
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#define AIO3_PWM nullptr
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#define AIO4_PIN PINA4
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#define AIO4_RPORT PINA
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#define AIO4_WPORT PORTA
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#define AIO4_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define AIO4_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#define AIO5_PIN PINA5
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#define AIO5_RPORT PINA
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#define AIO5_WPORT PORTA
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#define AIO5_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define AIO5_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#define AIO6_PIN PINA6
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#define AIO6_RPORT PINA
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#define AIO6_WPORT PORTA
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#define AIO6_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define AIO6_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#define AIO7_PIN PINA7
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#define AIO7_RPORT PINA
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#define AIO7_WPORT PORTA
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#define AIO7_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define AIO7_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA0
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#define PA0_PIN PINA0
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#define PA0_RPORT PINA
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#define PA0_WPORT PORTA
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#define PA0_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA0_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA1
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#define PA1_PIN PINA1
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#define PA1_RPORT PINA
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#define PA1_WPORT PORTA
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#define PA1_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA1_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA2
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#define PA2_PIN PINA2
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#define PA2_RPORT PINA
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#define PA2_WPORT PORTA
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#define PA2_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA2_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA3
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#define PA3_PIN PINA3
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#define PA3_RPORT PINA
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#define PA3_WPORT PORTA
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#define PA3_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA3_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA4
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#define PA4_PIN PINA4
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#define PA4_RPORT PINA
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#define PA4_WPORT PORTA
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#define PA4_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA4_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA5
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#define PA5_PIN PINA5
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#define PA5_RPORT PINA
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#define PA5_WPORT PORTA
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#define PA5_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA5_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA6
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#define PA6_PIN PINA6
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#define PA6_RPORT PINA
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#define PA6_WPORT PORTA
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#define PA6_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA6_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PA7
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#define PA7_PIN PINA7
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#define PA7_RPORT PINA
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#define PA7_WPORT PORTA
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#define PA7_DDR DDRA
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2019-05-09 18:45:55 +02:00
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#define PA7_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PB0
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#define PB0_PIN PINB0
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#define PB0_RPORT PINB
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#define PB0_WPORT PORTB
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#define PB0_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB0_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PB1
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#define PB1_PIN PINB1
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#define PB1_RPORT PINB
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#define PB1_WPORT PORTB
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#define PB1_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB1_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PB2
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#define PB2_PIN PINB2
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#define PB2_RPORT PINB
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#define PB2_WPORT PORTB
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#define PB2_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB2_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PB3
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#define PB3_PIN PINB3
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#define PB3_RPORT PINB
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#define PB3_WPORT PORTB
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#define PB3_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB3_PWM &OCR0A
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2017-05-21 16:42:39 +02:00
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#undef PB4
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#define PB4_PIN PINB4
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#define PB4_RPORT PINB
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#define PB4_WPORT PORTB
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#define PB4_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB4_PWM &OCR0B
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2017-05-21 16:42:39 +02:00
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#undef PB5
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#define PB5_PIN PINB5
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#define PB5_RPORT PINB
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#define PB5_WPORT PORTB
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#define PB5_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB5_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PB6
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#define PB6_PIN PINB6
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#define PB6_RPORT PINB
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#define PB6_WPORT PORTB
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#define PB6_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB6_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PB7
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#define PB7_PIN PINB7
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#define PB7_RPORT PINB
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#define PB7_WPORT PORTB
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#define PB7_DDR DDRB
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2019-05-09 18:45:55 +02:00
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#define PB7_PWM nullptr
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2017-05-21 16:42:39 +02:00
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#undef PC0
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#define PC0_PIN PINC0
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#define PC0_RPORT PINC
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#define PC0_WPORT PORTC
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#define PC0_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC1
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#define PC1_PIN PINC1
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#define PC1_RPORT PINC
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#define PC1_WPORT PORTC
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#define PC1_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC2
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#define PC2_PIN PINC2
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#define PC2_RPORT PINC
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#define PC2_WPORT PORTC
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#define PC2_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC3
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#define PC3_PIN PINC3
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#define PC3_RPORT PINC
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#define PC3_WPORT PORTC
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#define PC3_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC3_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC4
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#define PC4_PIN PINC4
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#define PC4_RPORT PINC
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#define PC4_WPORT PORTC
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#define PC4_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC4_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC5
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#define PC5_PIN PINC5
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#define PC5_RPORT PINC
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#define PC5_WPORT PORTC
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#define PC5_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC5_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC6
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#define PC6_PIN PINC6
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#define PC6_RPORT PINC
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#define PC6_WPORT PORTC
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#define PC6_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC6_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PC7
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#define PC7_PIN PINC7
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#define PC7_RPORT PINC
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#define PC7_WPORT PORTC
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#define PC7_DDR DDRC
|
2019-05-09 18:45:55 +02:00
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#define PC7_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD0
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#define PD0_PIN PIND0
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#define PD0_RPORT PIND
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#define PD0_WPORT PORTD
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#define PD0_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD0_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD1
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#define PD1_PIN PIND1
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#define PD1_RPORT PIND
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#define PD1_WPORT PORTD
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#define PD1_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD1_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD2
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#define PD2_PIN PIND2
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#define PD2_RPORT PIND
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#define PD2_WPORT PORTD
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#define PD2_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD2_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD3
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#define PD3_PIN PIND3
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#define PD3_RPORT PIND
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#define PD3_WPORT PORTD
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#define PD3_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD3_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD4
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#define PD4_PIN PIND4
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#define PD4_RPORT PIND
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#define PD4_WPORT PORTD
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#define PD4_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD4_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD5
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#define PD5_PIN PIND5
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#define PD5_RPORT PIND
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#define PD5_WPORT PORTD
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#define PD5_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD5_PWM nullptr
|
2017-05-21 16:42:39 +02:00
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#undef PD6
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#define PD6_PIN PIND6
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#define PD6_RPORT PIND
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#define PD6_WPORT PORTD
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#define PD6_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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|
#define PD6_PWM &OCR2B
|
2017-05-21 16:42:39 +02:00
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#undef PD7
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#define PD7_PIN PIND7
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#define PD7_RPORT PIND
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#define PD7_WPORT PORTD
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#define PD7_DDR DDRD
|
2019-05-09 18:45:55 +02:00
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#define PD7_PWM &OCR2A
|