From 9dd5390d7de65456a47285274903ca5b4ffc06eb Mon Sep 17 00:00:00 2001 From: Scott Lahteine Date: Wed, 27 Sep 2017 04:57:00 -0500 Subject: [PATCH] frameworks whitespace cleanup --- .../CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S | 26 ++++---- frameworks/CMSIS/LPC1768/driver/lpc17xx_i2c.c | 46 ++++++------- frameworks/CMSIS/LPC1768/driver/lpc17xx_i2s.c | 4 +- .../CMSIS/LPC1768/include/arm_common_tables.h | 64 +++++++++---------- .../CMSIS/LPC1768/include/core_cmFunc.h | 22 +++---- .../CMSIS/LPC1768/include/lpc17xx_iap.h | 6 +- .../CMSIS/LPC1768/include/system_LPC17xx.h | 12 ++-- frameworks/CMSIS/library.json | 6 +- 8 files changed, 93 insertions(+), 93 deletions(-) diff --git a/frameworks/CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S b/frameworks/CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S index 313e4177df..9ac4871e1c 100644 --- a/frameworks/CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S +++ b/frameworks/CMSIS/LPC1768/Re-ARM/startup_LPC17xx.S @@ -1,13 +1,13 @@ /* File: startup_ARMCM3.s - * Purpose: startup file for Cortex-M3/M4 devices. Should use with + * Purpose: startup file for Cortex-M3/M4 devices. Should use with * GNU Tools for ARM Embedded Processors * Version: V1.1 * Date: 17 June 2011 - * + * * Copyright (C) 2011 ARM Limited. All rights reserved. - * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF @@ -20,12 +20,12 @@ /* Memory Model The HEAP starts at the end of the DATA section and grows upward. - + The STACK starts at the end of the RAM and grows downward. - + The HEAP and stack STACK are only checked at compile time: (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - + This is just a check for the bare minimum for the Heap+Stack area before aborting compilation, it is not the run time limit: Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 @@ -59,7 +59,7 @@ __HeapBase: .size __HeapBase, . - __HeapBase __HeapLimit: .size __HeapLimit, . - __HeapLimit - + .section .isr_vector .align 2 .globl __isr_vector @@ -128,7 +128,7 @@ __isr_vector: .type Reset_Handler, %function Reset_Handler: /* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in + * of copy from/to are specified by following symbols evaluated in * linker script. * _etext: End of code section, i.e., begin of data sections to copy from. * __data_start__/__data_end__: RAM address range that data should be @@ -153,7 +153,7 @@ Reset_Handler: bx r0 .pool .size Reset_Handler, . - Reset_Handler - + /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ @@ -166,7 +166,7 @@ Reset_Handler: b . .size \handler_name, . - \handler_name .endm - + def_default_handler NMI_Handler def_default_handler HardFault_Handler def_default_handler MemManage_Handler @@ -177,7 +177,7 @@ Reset_Handler: def_default_handler PendSV_Handler def_default_handler SysTick_Handler def_default_handler Default_Handler - + def_default_handler WDT_IRQHandler def_default_handler TIMER0_IRQHandler def_default_handler TIMER1_IRQHandler diff --git a/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2c.c b/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2c.c index 485b57e000..99b29e017c 100644 --- a/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2c.c +++ b/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2c.c @@ -188,7 +188,7 @@ static uint32_t I2C_SendByte (LPC_I2C_TypeDef *I2Cx, uint8_t databyte) { return CodeStatus; } - + /* Make sure start bit is not active */ if (I2Cx->I2CONSET & I2C_I2CONSET_STA) { @@ -216,7 +216,7 @@ static uint32_t I2C_SendByte (LPC_I2C_TypeDef *I2Cx, uint8_t databyte) static uint32_t I2C_GetByte (LPC_I2C_TypeDef *I2Cx, uint8_t *retdat, Bool ack) { *retdat = (uint8_t) (I2Cx->I2DAT & I2C_I2DAT_BITMASK); - + if (ack == TRUE) { I2Cx->I2CONSET = I2C_I2CONSET_AA; @@ -227,7 +227,7 @@ static uint32_t I2C_GetByte (LPC_I2C_TypeDef *I2Cx, uint8_t *retdat, Bool ack) } I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; - + return (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK); } @@ -454,7 +454,7 @@ int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M uint8_t *rxdat; uint8_t tmp; int32_t Ret = I2C_OK; - + //get buffer to send/receive txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count]; rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count]; @@ -481,11 +481,11 @@ int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M break; case I2C_I2STAT_M_TX_SLAW_ACK: case I2C_I2STAT_M_TX_DAT_ACK: - + if(TransferCfg->tx_count < TransferCfg->tx_length) { I2C_SendByte(I2Cx, *txdat); - + txdat++; TransferCfg->tx_count++; @@ -497,7 +497,7 @@ int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M I2C_Stop(I2Cx); Ret = I2C_SEND_END; - + } break; case I2C_I2STAT_M_TX_DAT_NACK: @@ -537,7 +537,7 @@ int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M { Ret = I2C_RECV_END; } - + break; case I2C_I2STAT_M_RX_DAT_NACK: I2C_GetByte(I2Cx, &tmp, FALSE); @@ -559,7 +559,7 @@ int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; break; } - + return Ret; } @@ -592,7 +592,7 @@ int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_ //get buffer to send/receive txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count]; rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count]; - + switch (CodeStatus) { /* Reading phase -------------------------------------------------------- */ @@ -636,7 +636,7 @@ int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_ I2Cx->I2CONSET = I2C_I2CONSET_AA; I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; } - + break; /* DATA has been received, Only the first data byte will be received with ACK. Additional data will be received with NOT ACK. */ @@ -688,7 +688,7 @@ int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_ I2Cx->I2CONSET = I2C_I2CONSET_AA|I2C_I2CONSET_STA; I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; break; - + case I2C_I2STAT_S_TX_LAST_DAT_ACK: /* Data has been transmitted, NACK has been received, * that means there's no more data to send, exit now */ @@ -729,7 +729,7 @@ int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; Ret = I2C_STA_STO_RECV; break; - + /* No status information */ case I2C_I2STAT_NO_INF: /* Other status must be captured */ @@ -737,7 +737,7 @@ int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_ I2Cx->I2CONSET = I2C_I2CONSET_AA; I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; break; - + } return Ret; @@ -787,7 +787,7 @@ void I2C_MasterHandler(LPC_I2C_TypeDef *I2Cx) else if (Ret & I2C_SEND_END) { // If no need to wait for data from Slave - if(txrx_setup->rx_count >= (txrx_setup->rx_length)) + if(txrx_setup->rx_count >= (txrx_setup->rx_length)) { goto s_int_end; } @@ -799,7 +799,7 @@ void I2C_MasterHandler(LPC_I2C_TypeDef *I2Cx) return; } } - else if (Ret & I2C_RECV_END) + else if (Ret & I2C_RECV_END) { goto s_int_end; } @@ -815,7 +815,7 @@ s_int_end: I2Cx->I2CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; I2C_MasterComplete[i2cId] = TRUE; - + } @@ -874,7 +874,7 @@ handle_state: goto s_int_end; } } - } + } } else if(Ret &I2C_SEND_END) { @@ -937,7 +937,7 @@ retry: // Start command CodeStatus = I2C_Start(I2Cx); - + while(1) // send data first and then receive data from Slave. { Ret = I2C_MasterHanleStates(I2Cx, CodeStatus, TransferCfg); @@ -955,13 +955,13 @@ retry: else if( (Ret & I2C_BYTE_SENT) || (Ret & I2C_BYTE_RECV)) { - // Wait for sending ends + // Wait for sending ends while (!(I2Cx->I2CONSET & I2C_I2CONSET_SI)); } else if (Ret & I2C_SEND_END) // already send all data { // If no need to wait for data from Slave - if(TransferCfg->rx_count >= (TransferCfg->rx_length)) + if(TransferCfg->rx_count >= (TransferCfg->rx_length)) { break; } @@ -1037,7 +1037,7 @@ Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, I2C_S_SETUP_Type *TransferCf I2C_TRANSFER_OPT_Type Opt) { int32_t Ret = I2C_OK; - + uint32_t CodeStatus; uint32_t timeout; int32_t time_en; @@ -1052,7 +1052,7 @@ Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, I2C_S_SETUP_Type *TransferCf { /* Set AA bit to ACK command on I2C bus */ I2Cx->I2CONSET = I2C_I2CONSET_AA; - + /* Clear SI bit to be ready ... */ I2Cx->I2CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC|I2C_I2CONCLR_STOC); diff --git a/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2s.c b/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2s.c index 359bf8218e..f57fd2f1be 100644 --- a/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2s.c +++ b/frameworks/CMSIS/LPC1768/driver/lpc17xx_i2s.c @@ -331,7 +331,7 @@ Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode) { uint16_t dif; uint16_t x_divide, y_divide; uint16_t err, ErrorOptimal = 0xFFFF; - + uint32_t N; CHECK_PARAM(PARAM_I2Sx(I2Sx)); @@ -360,7 +360,7 @@ Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode) { * The formula is: * I2S_MCLK = PCLK_I2S * (X/Y) / 2 * In that, Y must be greater than or equal to X. X should divides evenly - * into Y. + * into Y. * We have: * I2S_MCLK = Freq * channel*wordwidth * (I2STXBITRATE+1); * So: (X/Y) = (Freq * channel*wordwidth * (I2STXBITRATE+1))*2/PCLK_I2S diff --git a/frameworks/CMSIS/LPC1768/include/arm_common_tables.h b/frameworks/CMSIS/LPC1768/include/arm_common_tables.h index 7245c4f12b..d55c46349f 100644 --- a/frameworks/CMSIS/LPC1768/include/arm_common_tables.h +++ b/frameworks/CMSIS/LPC1768/include/arm_common_tables.h @@ -1,35 +1,35 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 11. November 2010 +* $Revision: V1.0.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* * Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern uint16_t armBitRevTable[256]; -extern q15_t armRecipTableQ15[64]; -extern q31_t armRecipTableQ31[64]; +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern uint16_t armBitRevTable[256]; +extern q15_t armRecipTableQ15[64]; +extern q31_t armRecipTableQ31[64]; extern const q31_t realCoefAQ31[1024]; extern const q31_t realCoefBQ31[1024]; - -#endif /* ARM_COMMON_TABLES_H */ + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/frameworks/CMSIS/LPC1768/include/core_cmFunc.h b/frameworks/CMSIS/LPC1768/include/core_cmFunc.h index 88819f9dd1..e29757aef7 100644 --- a/frameworks/CMSIS/LPC1768/include/core_cmFunc.h +++ b/frameworks/CMSIS/LPC1768/include/core_cmFunc.h @@ -8,9 +8,9 @@ * Copyright (C) 2009-2011 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED @@ -26,7 +26,7 @@ /* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface +/** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ @@ -182,7 +182,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask) register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } - + #if (__CORTEX_M >= 0x03) @@ -226,7 +226,7 @@ static __INLINE void __set_BASEPRI(uint32_t basePri) register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } - + /** \brief Get Fault Mask @@ -407,7 +407,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); return(result); } - + /** \brief Set Process Stack Pointer @@ -434,7 +434,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); return(result); } - + /** \brief Set Main Stack Pointer @@ -473,7 +473,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p { __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); } - + #if (__CORTEX_M >= 0x03) @@ -508,7 +508,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) { uint32_t result; - + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } @@ -535,7 +535,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; - + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } diff --git a/frameworks/CMSIS/LPC1768/include/lpc17xx_iap.h b/frameworks/CMSIS/LPC1768/include/lpc17xx_iap.h index 24b2935871..7a53c17ba1 100644 --- a/frameworks/CMSIS/LPC1768/include/lpc17xx_iap.h +++ b/frameworks/CMSIS/LPC1768/include/lpc17xx_iap.h @@ -7,7 +7,7 @@ * @version 1.0 * @date 18. April. 2012 * @author NXP MCU SW Application Team -* +* * Copyright(C) 2011, NXP Semiconductor * All rights reserved. * @@ -112,7 +112,7 @@ typedef struct { /** * @} */ - + /* Public Functions ----------------------------------------------------------- */ /** @defgroup IAP_Public_Functions IAP Public Functions * @{ @@ -128,7 +128,7 @@ IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE si IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec); /** Blank check sectors */ IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec, - uint32_t *first_nblank_loc, + uint32_t *first_nblank_loc, uint32_t *first_nblank_val); /** Read part identification number */ IAP_STATUS_CODE ReadPartID(uint32_t *partID); diff --git a/frameworks/CMSIS/LPC1768/include/system_LPC17xx.h b/frameworks/CMSIS/LPC1768/include/system_LPC17xx.h index c8e522f0bc..7aa7ad2e00 100755 --- a/frameworks/CMSIS/LPC1768/include/system_LPC17xx.h +++ b/frameworks/CMSIS/LPC1768/include/system_LPC17xx.h @@ -1,16 +1,16 @@ /****************************************************************************** * @file: system_LPC17xx.h * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File - * for the NXP LPC17xx Device Series + * for the NXP LPC17xx Device Series * @version: V1.02 * @date: 27. July 2009 *---------------------------------------------------------------------------- * * Copyright (C) 2009 ARM Limited. All rights reserved. * - * ARM Limited (ARM) is supplying this software for use with Cortex-M3 - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF @@ -26,7 +26,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ @@ -48,7 +48,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/frameworks/CMSIS/library.json b/frameworks/CMSIS/library.json index 4edc7226c7..7b30a2f203 100644 --- a/frameworks/CMSIS/library.json +++ b/frameworks/CMSIS/library.json @@ -1,9 +1,9 @@ { - "name": "CMSIS-LPC1768", + "name": "CMSIS-LPC1768", "version": "0.0.0", - "frameworks": [], + "frameworks": [], "platforms": [ - "nxplpc", + "nxplpc", "ststm32" ], "description": "CMSIS library for LPC1768",