![Scott Lahteine](/assets/img/avatar_default.png)
* Consolidate variant scripts * Rename Marlin-local boards * Simplify variants where possible * Rename variants * CHITU_F103 and MEEB_3DP: Maple platform `platformio-build-stm32f1.py` uses the 'board' name, not 'board_build.variant' so folder names match 'board' and not `board_build.variant`.
577 lines
15 KiB
Plaintext
577 lines
15 KiB
Plaintext
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adc10_sam3u.o:
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adc12_sam3u.o:
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adc_sam3snxa.o:
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pio.o:
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00000000 T PIO_Clear
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00000000 T PIO_Configure
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00000000 T PIO_DisableInterrupt
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00000000 T PIO_Get
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00000000 T PIO_GetOutputDataStatus
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00000000 T PIO_PullUp
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00000000 T PIO_Set
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00000000 T PIO_SetDebounceFilter
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00000000 T PIO_SetInput
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00000000 T PIO_SetOutput
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00000000 T PIO_SetPeripheral
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pmc.o:
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00000000 T pmc_clr_fast_startup_input
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00000000 T pmc_disable_all_pck
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00000000 T pmc_disable_all_periph_clk
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00000000 T pmc_disable_interrupt
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00000000 T pmc_disable_pck
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00000000 T pmc_disable_periph_clk
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00000000 T pmc_disable_pllack
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00000000 T pmc_disable_udpck
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00000000 T pmc_disable_upll_clock
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00000000 T pmc_enable_all_pck
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00000000 T pmc_enable_all_periph_clk
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00000000 T pmc_enable_backupmode
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00000000 T pmc_enable_interrupt
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00000000 T pmc_enable_pck
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00000000 T pmc_enable_periph_clk
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00000000 T pmc_enable_pllack
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00000000 T pmc_enable_sleepmode
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00000000 T pmc_enable_udpck
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00000000 T pmc_enable_upll_clock
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00000000 T pmc_enable_waitmode
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00000000 T pmc_get_interrupt_mask
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00000000 T pmc_get_status
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00000000 T pmc_get_writeprotect_status
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00000000 T pmc_is_locked_pllack
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00000000 T pmc_is_locked_upll
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00000000 T pmc_is_pck_enabled
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00000000 T pmc_is_periph_clk_enabled
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00000000 T pmc_mck_set_prescaler
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00000000 T pmc_mck_set_source
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00000000 T pmc_osc_disable_fastrc
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00000000 T pmc_osc_disable_xtal
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00000000 T pmc_osc_enable_fastrc
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00000000 T pmc_osc_is_ready_32kxtal
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00000000 T pmc_osc_is_ready_mainck
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00000000 T pmc_pck_set_prescaler
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00000000 T pmc_pck_set_source
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00000000 T pmc_set_fast_startup_input
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00000000 T pmc_set_writeprotect
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00000000 T pmc_switch_mainck_to_fastrc
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00000000 T pmc_switch_mainck_to_xtal
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00000000 T pmc_switch_mck_to_mainck
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00000000 T pmc_switch_mck_to_pllack
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00000000 T pmc_switch_mck_to_sclk
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00000000 T pmc_switch_mck_to_upllck
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00000000 T pmc_switch_pck_to_mainck
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00000000 T pmc_switch_pck_to_pllack
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00000000 T pmc_switch_pck_to_sclk
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00000000 T pmc_switch_pck_to_upllck
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00000000 T pmc_switch_sclk_to_32kxtal
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00000000 T pmc_switch_udpck_to_pllack
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00000000 T pmc_switch_udpck_to_upllck
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pwmc.o:
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00000000 t FindClockConfiguration
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00000000 T PWMC_ConfigureChannel
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00000000 T PWMC_ConfigureChannelExt
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00000000 T PWMC_ConfigureClocks
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00000000 T PWMC_ConfigureComparisonUnit
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00000000 T PWMC_ConfigureEventLineMode
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00000000 T PWMC_ConfigureSyncChannel
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00000000 T PWMC_DisableChannel
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00000000 T PWMC_DisableChannelIt
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00000000 T PWMC_DisableIt
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00000000 T PWMC_DisableOverrideOutput
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00000000 T PWMC_EnableChannel
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00000000 T PWMC_EnableChannelIt
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00000000 T PWMC_EnableFaultProtection
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00000000 T PWMC_EnableIt
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00000000 T PWMC_EnableOverrideOutput
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00000000 T PWMC_FaultClear
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00000000 T PWMC_SetDeadTime
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00000000 T PWMC_SetDutyCycle
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00000000 T PWMC_SetFaultMode
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00000000 T PWMC_SetFaultProtectionValue
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00000000 T PWMC_SetOverrideValue
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00000000 T PWMC_SetPeriod
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00000000 T PWMC_SetSyncChannelUpdatePeriod
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00000000 T PWMC_SetSyncChannelUpdateUnlock
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00000000 T PWMC_WriteBuffer
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U __assert_func
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00000000 r __func__.6793
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00000000 r __func__.6804
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00000000 r __func__.6819
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00000000 r __func__.6830
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00000000 r __func__.6841
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00000000 r __func__.6848
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00000000 r __func__.6932
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00000000 r __func__.6938
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rtc.o:
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00000000 T RTC_ClearSCCR
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00000000 T RTC_DisableIt
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00000000 T RTC_EnableIt
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00000000 T RTC_GetDate
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00000000 T RTC_GetHourMode
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00000000 T RTC_GetSR
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00000000 T RTC_GetTime
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00000000 T RTC_SetDate
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00000000 T RTC_SetDateAlarm
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00000000 T RTC_SetHourMode
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00000000 T RTC_SetTime
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00000000 T RTC_SetTimeAlarm
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U __assert_func
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00000000 r __func__.6790
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00000000 r __func__.6799
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00000000 r __func__.6804
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rtt.o:
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00000000 T RTT_EnableIT
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00000000 T RTT_GetStatus
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00000000 T RTT_GetTime
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00000000 T RTT_SetAlarm
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00000000 T RTT_SetPrescaler
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U __assert_func
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00000000 r __func__.6797
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00000000 r __func__.6805
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spi.o:
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00000000 T SPI_Configure
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00000000 T SPI_ConfigureNPCS
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00000000 T SPI_Disable
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00000000 T SPI_DisableIt
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00000000 T SPI_Enable
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00000000 T SPI_EnableIt
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00000000 T SPI_GetStatus
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00000000 T SPI_IsFinished
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00000000 T SPI_Read
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00000000 T SPI_Write
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U pmc_enable_periph_clk
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tc.o:
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00000000 T TC_Configure
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00000000 T TC_FindMckDivisor
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00000000 T TC_GetStatus
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00000000 T TC_ReadCV
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00000000 T TC_SetRA
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00000000 T TC_SetRB
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00000000 T TC_SetRC
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00000000 T TC_Start
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00000000 T TC_Stop
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U __assert_func
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00000000 r __func__.6792
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00000000 r __func__.6798
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00000000 r __func__.6804
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timetick.o:
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00000000 T GetTickCount
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00000000 T Sleep
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00000000 T TimeTick_Configure
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00000000 T TimeTick_Increment
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00000000 T Wait
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00000000 b _dwTickCount
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twi.o:
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00000000 T TWI_ByteReceived
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00000000 T TWI_ByteSent
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00000000 T TWI_ConfigureMaster
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00000000 T TWI_ConfigureSlave
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00000000 T TWI_Disable
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00000000 T TWI_DisableIt
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00000000 T TWI_EnableIt
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00000000 T TWI_GetMaskedStatus
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00000000 T TWI_GetStatus
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00000000 T TWI_ReadByte
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00000000 T TWI_SendSTOPCondition
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00000000 T TWI_SetClock
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00000000 T TWI_StartRead
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00000000 T TWI_StartWrite
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00000000 T TWI_Stop
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00000000 T TWI_TransferComplete
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00000000 T TWI_WriteByte
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U __assert_func
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00000000 r __func__.7151
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00000000 r __func__.7157
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00000000 r __func__.7172
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00000000 r __func__.7176
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00000000 r __func__.7184
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00000000 r __func__.7191
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00000000 r __func__.7195
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00000000 r __func__.7200
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00000000 r __func__.7208
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00000000 r __func__.7222
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00000000 r __func__.7227
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00000000 r __func__.7231
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00000000 r __func__.7236
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00000000 r __func__.7240
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usart.o:
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00000000 T USART_Configure
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00000000 T USART_DisableIt
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00000000 T USART_EnableIt
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00000000 T USART_GetChar
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00000000 T USART_GetStatus
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00000000 T USART_IsDataAvailable
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00000000 T USART_IsRxReady
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00000000 T USART_PutChar
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00000000 T USART_Read
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00000000 T USART_ReadBuffer
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00000000 T USART_SetIrdaFilter
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00000000 T USART_SetReceiverEnabled
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00000000 T USART_SetTransmitterEnabled
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00000000 T USART_Write
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00000000 T USART_WriteBuffer
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U __assert_func
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00000000 r __func__.7068
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wdt.o:
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00000000 T WDT_Disable
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00000000 T WDT_Enable
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00000000 T WDT_GetPeriod
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00000000 T WDT_GetStatus
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00000000 T WDT_Restart
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system_sam3xa.o:
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00000000 D SystemCoreClock
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00000000 T SystemCoreClockUpdate
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00000000 T SystemInit
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00000000 T system_init_flash
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startup_sam3xa.o:
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U ADC_Handler
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U BusFault_Handler
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U CAN0_Handler
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U CAN1_Handler
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U DACC_Handler
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U DMAC_Handler
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U DebugMon_Handler
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U EFC0_Handler
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U EFC1_Handler
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U EMAC_Handler
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U HSMCI_Handler
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U HardFault_Handler
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U MemManage_Handler
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U NMI_Handler
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U PIOA_Handler
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U PIOB_Handler
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U PIOC_Handler
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U PIOD_Handler
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U PMC_Handler
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U PWM_Handler
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U PendSV_Handler
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U RSTC_Handler
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U RTC_Handler
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U RTT_Handler
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00000000 T Reset_Handler
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U SMC_Handler
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U SPI0_Handler
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U SSC_Handler
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U SUPC_Handler
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U SVC_Handler
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U SysTick_Handler
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U TC0_Handler
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U TC1_Handler
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U TC2_Handler
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U TC3_Handler
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U TC4_Handler
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U TC5_Handler
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U TC6_Handler
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U TC7_Handler
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U TC8_Handler
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U TRNG_Handler
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U TWI0_Handler
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U TWI1_Handler
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U UART_Handler
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U UOTGHS_Handler
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U USART0_Handler
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U USART1_Handler
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U USART2_Handler
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U USART3_Handler
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U UsageFault_Handler
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U WDT_Handler
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U _erelocate
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U _estack
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U _etext
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U _ezero
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U _sfixed
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U _srelocate
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U _szero
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00000000 R exception_table
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U main
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adc.o:
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00000000 T adc_configure_power_save
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00000000 T adc_configure_sequence
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00000000 T adc_configure_timing
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00000000 T adc_configure_trigger
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00000000 T adc_disable_all_channel
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00000000 T adc_disable_anch
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00000000 T adc_disable_channel
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00000000 T adc_disable_channel_differential_input
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00000000 T adc_disable_channel_input_offset
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00000000 T adc_disable_interrupt
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00000000 T adc_disable_tag
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00000000 T adc_disable_ts
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00000000 T adc_enable_all_channel
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00000000 T adc_enable_anch
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00000000 T adc_enable_channel
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00000000 T adc_enable_channel_differential_input
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00000000 T adc_enable_channel_input_offset
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00000000 T adc_enable_interrupt
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00000000 T adc_enable_tag
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00000000 T adc_enable_ts
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00000000 T adc_get_actual_adc_clock
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00000000 T adc_get_channel_status
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00000000 T adc_get_channel_value
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00000000 T adc_get_comparison_mode
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00000000 T adc_get_interrupt_mask
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00000000 T adc_get_latest_value
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00000000 T adc_get_overrun_status
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00000000 T adc_get_pdc_base
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00000000 T adc_get_status
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00000000 T adc_get_tag
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00000000 T adc_get_writeprotect_status
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00000000 T adc_init
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00000000 T adc_set_bias_current
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00000000 T adc_set_channel_input_gain
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00000000 T adc_set_comparison_channel
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00000000 T adc_set_comparison_mode
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00000000 T adc_set_comparison_window
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00000000 T adc_set_resolution
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00000000 T adc_set_writeprotect
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00000000 T adc_start
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00000000 T adc_start_sequencer
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00000000 T adc_stop
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00000000 T adc_stop_sequencer
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udp.o:
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udphs.o:
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uotghs.o:
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00000000 T UOTGHS_Handler
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00000000 B gpf_isr
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interrupt_sam_nvic.o:
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00000000 D g_interrupt_enabled
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uotghs_device.o:
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00000000 T UDD_Attach
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00000000 T UDD_ClearIN
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00000000 T UDD_ClearOUT
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00000000 T UDD_ClearSetupInt
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00000000 T UDD_Detach
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00000000 T UDD_FifoByteCount
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00000000 T UDD_GetFrameNumber
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00000000 T UDD_Init
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00000000 T UDD_InitEP
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00000000 T UDD_InitEndpoints
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00000000 T UDD_ReadWriteAllowed
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00000000 T UDD_ReceivedSetupInt
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00000000 T UDD_Recv
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00000000 T UDD_Recv8
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00000000 T UDD_ReleaseRX
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00000000 T UDD_ReleaseTX
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00000000 T UDD_Send
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00000000 T UDD_Send8
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00000000 T UDD_SetAddress
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00000000 T UDD_SetStack
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00000000 T UDD_Stall
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00000000 T UDD_WaitForINOrOUT
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00000000 T UDD_WaitIN
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00000000 T UDD_WaitOUT
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U g_interrupt_enabled
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U gpf_isr
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U pmc_enable_periph_clk
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U pmc_enable_udpck
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U pmc_enable_upll_clock
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U pmc_switch_udpck_to_upllck
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00000000 b ul_recv_fifo_ptr
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00000000 b ul_send_fifo_ptr
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uotghs_host.o:
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00000000 T UHD_BusReset
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00000000 T UHD_GetVBUSState
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00000000 t UHD_ISR
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00000000 T UHD_Init
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00000000 T UHD_Pipe0_Alloc
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00000000 T UHD_Pipe_Alloc
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00000000 T UHD_Pipe_Free
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00000000 T UHD_Pipe_Is_Transfer_Complete
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00000000 T UHD_Pipe_Read
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00000000 T UHD_Pipe_Send
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00000000 T UHD_Pipe_Write
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00000000 T UHD_SetStack
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U g_interrupt_enabled
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U gpf_isr
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U pmc_enable_periph_clk
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U pmc_enable_udpck
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U pmc_enable_upll_clock
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U pmc_switch_udpck_to_upllck
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00000000 b uhd_state
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dacc.o:
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00000000 T dacc_disable_channel
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00000000 T dacc_disable_interrupt
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00000000 T dacc_disable_trigger
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00000000 T dacc_enable_channel
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00000000 T dacc_enable_flexible_selection
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00000000 T dacc_enable_interrupt
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00000000 T dacc_get_analog_control
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00000000 T dacc_get_channel_status
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00000000 T dacc_get_interrupt_mask
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00000000 T dacc_get_interrupt_status
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00000000 T dacc_get_pdc_base
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00000000 T dacc_get_writeprotect_status
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00000000 T dacc_reset
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00000000 T dacc_set_analog_control
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00000000 T dacc_set_channel_selection
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00000000 T dacc_set_power_save
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00000000 T dacc_set_timing
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00000000 T dacc_set_transfer_mode
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00000000 T dacc_set_trigger
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00000000 T dacc_set_writeprotect
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00000000 T dacc_write_conversion_data
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can.o:
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00000000 R can_bit_time
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00000000 T can_disable
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00000000 T can_disable_autobaud_listen_mode
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00000000 T can_disable_interrupt
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00000000 T can_disable_low_power_mode
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00000000 T can_disable_overload_frame
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00000000 T can_disable_time_triggered_mode
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00000000 T can_disable_timer_freeze
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00000000 T can_disable_tx_repeat
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00000000 T can_enable
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00000000 T can_enable_autobaud_listen_mode
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00000000 T can_enable_interrupt
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00000000 T can_enable_low_power_mode
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00000000 T can_enable_overload_frame
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00000000 T can_enable_time_triggered_mode
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00000000 T can_enable_timer_freeze
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00000000 T can_enable_tx_repeat
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00000000 T can_get_internal_timer_value
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00000000 T can_get_interrupt_mask
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00000000 T can_get_rx_error_cnt
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00000000 T can_get_status
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00000000 T can_get_timestamp_value
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00000000 T can_get_tx_error_cnt
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00000000 T can_global_send_abort_cmd
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00000000 T can_global_send_transfer_cmd
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00000000 T can_init
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00000000 T can_mailbox_get_status
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00000000 T can_mailbox_init
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00000000 T can_mailbox_read
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00000000 T can_mailbox_send_abort_cmd
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00000000 T can_mailbox_send_transfer_cmd
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00000000 T can_mailbox_set_timemark
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00000000 T can_mailbox_tx_remote_frame
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00000000 T can_mailbox_write
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00000000 T can_reset_all_mailbox
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00000000 T can_reset_internal_timer
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00000000 T can_reset_mailbox_data
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00000000 T can_set_rx_sync_stage
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00000000 T can_set_timestamp_capture_point
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U memset
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efc.o:
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00000000 T efc_disable_frdy_interrupt
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00000000 T efc_enable_frdy_interrupt
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00000000 T efc_get_flash_access_mode
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00000000 T efc_get_result
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00000000 T efc_get_status
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00000000 T efc_get_wait_state
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00000000 T efc_init
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00000000 T efc_perform_command
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0000006c T efc_perform_fcr
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00000000 T efc_perform_read_sequence
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00000000 T efc_set_flash_access_mode
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00000000 T efc_set_wait_state
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00000068 T efc_write_fmr
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00000000 b iap_perform_command.7049
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gpbr.o:
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00000000 T gpbr_read
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00000000 T gpbr_write
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ssc.o:
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U memset
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00000000 T ssc_disable_interrupt
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00000000 T ssc_disable_rx
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00000000 T ssc_disable_tx
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00000000 T ssc_disable_tx_frame_sync_data
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00000000 T ssc_enable_interrupt
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00000000 T ssc_enable_rx
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00000000 T ssc_enable_tx
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00000000 T ssc_enable_tx_frame_sync_data
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00000000 T ssc_get_interrupt_mask
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00000000 T ssc_get_rx_access
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00000000 T ssc_get_rx_compare
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00000000 T ssc_get_status
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00000000 T ssc_get_tx_access
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00000000 T ssc_get_writeprotect_status
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00000000 T ssc_i2s_set_receiver
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00000000 T ssc_i2s_set_transmitter
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00000000 T ssc_is_rx_enabled
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00000000 T ssc_is_rx_ready
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00000000 T ssc_is_tx_empty
|
|
00000000 T ssc_is_tx_enabled
|
|
00000000 T ssc_is_tx_ready
|
|
00000000 T ssc_read
|
|
00000000 T ssc_read_sync_data
|
|
00000000 T ssc_reset
|
|
00000000 T ssc_set_clock_divider
|
|
00000000 T ssc_set_loop_mode
|
|
00000000 T ssc_set_normal_mode
|
|
00000000 T ssc_set_receiver
|
|
00000000 T ssc_set_rx_compare
|
|
00000000 T ssc_set_rx_stop_selection
|
|
00000000 T ssc_set_td_default_level
|
|
00000000 T ssc_set_transmitter
|
|
00000000 T ssc_set_writeprotect
|
|
00000000 T ssc_write
|
|
00000000 T ssc_write_sync_data
|
|
|
|
trng.o:
|
|
00000000 T trng_disable
|
|
00000000 T trng_disable_interrupt
|
|
00000000 T trng_enable
|
|
00000000 T trng_enable_interrupt
|
|
00000000 T trng_get_interrupt_mask
|
|
00000000 T trng_get_interrupt_status
|
|
00000000 T trng_read_output_data
|
|
|
|
rstc.o:
|
|
00000000 T rstc_disable_user_reset
|
|
00000000 T rstc_disable_user_reset_interrupt
|
|
00000000 T rstc_enable_user_reset
|
|
00000000 T rstc_enable_user_reset_interrupt
|
|
00000000 T rstc_get_reset_cause
|
|
00000000 T rstc_get_status
|
|
00000000 T rstc_reset_extern
|
|
00000000 T rstc_set_external_reset
|
|
00000000 T rstc_start_software_reset
|
|
|
|
emac.o:
|
|
00000000 t circ_inc
|
|
00000000 T emac_dev_get_tx_load
|
|
00000000 T emac_dev_init
|
|
00000000 T emac_dev_read
|
|
00000000 T emac_dev_reset
|
|
00000000 T emac_dev_set_rx_callback
|
|
00000000 T emac_dev_set_tx_wakeup_callback
|
|
00000000 T emac_dev_write
|
|
00000000 T emac_handler
|
|
00000000 T emac_phy_read
|
|
00000000 T emac_phy_write
|
|
00000000 t emac_reset_rx_mem
|
|
00000000 t emac_reset_tx_mem
|
|
00000000 b gs_rx_desc
|
|
00000000 b gs_tx_callback
|
|
00000000 b gs_tx_desc
|
|
00000000 b gs_uc_rx_buffer
|
|
00000000 b gs_uc_tx_buffer
|
|
U memcpy
|