etagle 0566badcef Add memory barrier, optimal interrupt on-off ... Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)		2018-05-20 02:39:34 -05:00
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backtrace	Move backtrace to the HAL folder (#10790)	2018-05-20 01:33:21 -05:00
HAL_AVR	Use assembly for AVR ISR vectors	2018-05-20 01:58:51 -05:00
HAL_DUE	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
HAL_LPC1768	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
HAL_STM32F1	Reorder HAL timer header items	2018-05-13 16:50:39 -05:00
HAL_STM32F4	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
HAL_STM32F7	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
HAL_TEENSY35_36	Add memory barrier, optimal interrupt on-off	2018-05-20 02:39:34 -05:00
Delay.h	Followup to HAL optimizations and delays	2018-05-13 00:46:23 -05:00
HAL_SPI.h	Preliminary cleanup of #include structure (#9763)	2018-02-23 00:52:52 -06:00
I2cEeprom.cpp	Fix missed includes from HAL macro patch (#10416)	2018-04-15 18:27:34 -05:00
math_32bit.h	Convert custom maths to inlines (#10728)	2018-05-13 08:10:08 -05:00
persistent_store_api.h	Add MarlinSettings::validate()	2018-01-05 14:35:24 -06:00
platforms.h	Strip trailing spaces	2018-04-23 18:00:43 -05:00
servo_private.h	Apply some formatting	2017-11-18 03:12:30 -06:00
servo.cpp	Smarter MIN, MAX, ABS macros	2018-05-13 04:52:56 -05:00
servo.h	[2.0.x] HAL for STM32F4 (#10434)	2018-04-17 17:33:29 -05:00
SpiEeprom.cpp	Fix missed includes from HAL macro patch (#10416)	2018-04-15 18:27:34 -05:00