226 lines
9.0 KiB
C++
226 lines
9.0 KiB
C++
/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2016, 2017 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* u8g_dev_st7565_64128n_HAL.c (Displaytech)
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*
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* Universal 8bit Graphics Library
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*
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* Copyright (c) 2011, olikraus@gmail.com
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "../../inc/MarlinConfig.h"
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#if ENABLED(DOGLCD)
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#include <U8glib.h>
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#include "HAL_LCD_com_defines.h"
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#define WIDTH 128
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#define HEIGHT 64
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#define PAGE_HEIGHT 8
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/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
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static const uint8_t u8g_dev_st7565_64128n_HAL_init_seq[] PROGMEM = {
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U8G_ESC_CS(0), // disable chip
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U8G_ESC_ADR(0), // instruction mode
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U8G_ESC_CS(1), // enable chip
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U8G_ESC_RST(15), // do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
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0x0A2, // 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet)
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0x0A0, // Normal ADC Select (according to Displaytech 64128N datasheet)
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0x0c8, // common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1
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0x040, // Display start line for Displaytech 64128N
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0x028 | 0x04, // power control: turn on voltage converter
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U8G_ESC_DLY(50), // delay 50 ms
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0x028 | 0x06, // power control: turn on voltage regulator
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U8G_ESC_DLY(50), // delay 50 ms
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0x028 | 0x07, // power control: turn on voltage follower
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U8G_ESC_DLY(50), // delay 50 ms
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0x010, // Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N
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0x0a6, // display normal, bit val 0: LCD pixel off.
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0x081, // set contrast
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0x01e, // Contrast value. Setting for controlling brightness of Displaytech 64128N
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0x0af, // display on
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U8G_ESC_DLY(100), // delay 100 ms
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0x0a5, // display all points, ST7565
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U8G_ESC_DLY(100), // delay 100 ms
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U8G_ESC_DLY(100), // delay 100 ms
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0x0a4, // normal display
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U8G_ESC_CS(0), // disable chip
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U8G_ESC_END // end of sequence
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};
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static const uint8_t u8g_dev_st7565_64128n_HAL_data_start[] PROGMEM = {
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U8G_ESC_ADR(0), // instruction mode
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U8G_ESC_CS(1), // enable chip
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0x010, // set upper 4 bit of the col adr to 0x10
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0x000, // set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N
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U8G_ESC_END // end of sequence
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};
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static const uint8_t u8g_dev_st7565_64128n_HAL_sleep_on[] PROGMEM = {
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U8G_ESC_ADR(0), // instruction mode
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U8G_ESC_CS(1), // enable chip
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0x0ac, // static indicator off
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0x000, // indicator register set (not sure if this is required)
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0x0ae, // display off
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0x0a5, // all points on
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U8G_ESC_CS(0), // disable chip, bugfix 12 nov 2014
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U8G_ESC_END // end of sequence
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};
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static const uint8_t u8g_dev_st7565_64128n_HAL_sleep_off[] PROGMEM = {
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U8G_ESC_ADR(0), // instruction mode
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U8G_ESC_CS(1), // enable chip
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0x0a4, // all points off
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0x0af, // display on
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U8G_ESC_DLY(50), // delay 50 ms
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U8G_ESC_CS(0), // disable chip, bugfix 12 nov 2014
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U8G_ESC_END // end of sequence
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};
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uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
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switch(msg) {
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT: {
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
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return 0;
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u8g_SetChipSelect(u8g, dev, 0);
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}
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break;
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case U8G_DEV_MSG_CONTRAST:
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u8g_SetChipSelect(u8g, dev, 1);
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u8g_SetAddress(u8g, dev, 0); /* instruction mode */
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u8g_WriteByte(u8g, dev, 0x081);
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u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
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u8g_SetChipSelect(u8g, dev, 0);
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return 1;
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case U8G_DEV_MSG_SLEEP_ON:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_sleep_on);
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_sleep_off);
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return 1;
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}
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return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
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}
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uint8_t u8g_dev_st7565_64128n_HAL_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
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switch(msg) {
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case U8G_DEV_MSG_INIT:
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u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_init_seq);
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break;
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case U8G_DEV_MSG_STOP:
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break;
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case U8G_DEV_MSG_PAGE_NEXT: {
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u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)pb->buf);
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u8g_SetChipSelect(u8g, dev, 0);
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_data_start);
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u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
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u8g_SetAddress(u8g, dev, 1); /* data mode */
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u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
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u8g_SetChipSelect(u8g, dev, 0);
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}
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break;
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case U8G_DEV_MSG_CONTRAST:
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u8g_SetChipSelect(u8g, dev, 1);
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u8g_SetAddress(u8g, dev, 0); /* instruction mode */
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u8g_WriteByte(u8g, dev, 0x081);
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u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
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u8g_SetChipSelect(u8g, dev, 0);
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return 1;
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case U8G_DEV_MSG_SLEEP_ON:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_sleep_on);
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_sleep_off);
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return 1;
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}
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return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
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}
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U8G_PB_DEV(u8g_dev_st7565_64128n_HAL_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_HAL_fn, U8G_COM_HAL_SW_SPI_FN);
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uint8_t u8g_dev_st7565_64128n_HAL_2x_buf[WIDTH*2] U8G_NOCOMMON ;
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u8g_pb_t u8g_dev_st7565_64128n_HAL_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_64128n_HAL_2x_buf};
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u8g_dev_t u8g_dev_st7565_64128n_HAL_2x_sw_spi = { u8g_dev_st7565_64128n_HAL_2x_fn, &u8g_dev_st7565_64128n_HAL_2x_pb, U8G_COM_HAL_SW_SPI_FN };
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U8G_PB_DEV(u8g_dev_st7565_64128n_HAL_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_HAL_fn, U8G_COM_HAL_HW_SPI_FN);
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u8g_dev_t u8g_dev_st7565_64128n_HAL_2x_hw_spi = { u8g_dev_st7565_64128n_HAL_2x_fn, &u8g_dev_st7565_64128n_HAL_2x_pb, U8G_COM_HAL_HW_SPI_FN };
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#endif // DOGLCD
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