0566badcef
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
115 lines
4.1 KiB
C++
115 lines
4.1 KiB
C++
/* **************************************************************************
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Marlin 3D Printer Firmware
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Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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Copyright (c) 2016 Bob Cousins bobcousins42@googlemail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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****************************************************************************/
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/**
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* Teensy3.5 __MK64FX512__
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* Teensy3.6 __MK66FX1M0__
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*/
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#if defined(__MK64FX512__) || defined(__MK66FX1M0__)
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#include "HAL.h"
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#include "HAL_timers_Teensy.h"
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/** \brief Instruction Synchronization Barrier
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Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or
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memory, after the instruction has been completed.
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*/
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FORCE_INLINE static void __ISB(void) {
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__asm__ __volatile__("isb 0xF":::"memory");
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}
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/** \brief Data Synchronization Barrier
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This function acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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FORCE_INLINE static void __DSB(void) {
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__asm__ __volatile__("dsb 0xF":::"memory");
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}
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void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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switch (timer_num) {
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case 0:
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FTM0_MODE = FTM_MODE_WPDIS | FTM_MODE_FTMEN;
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FTM0_SC = 0x00; // Set this to zero before changing the modulus
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FTM0_CNT = 0x0000; // Reset the count to zero
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FTM0_MOD = 0xFFFF; // max modulus = 65535
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FTM0_C0V = FTM0_TIMER_RATE / frequency; // Initial FTM Channel 0 compare value
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FTM0_SC = (FTM_SC_CLKS(0b1) & FTM_SC_CLKS_MASK) | (FTM_SC_PS(FTM0_TIMER_PRESCALE_BITS) & FTM_SC_PS_MASK); // Bus clock 60MHz divided by prescaler 8
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FTM0_C0SC = FTM_CSC_CHIE | FTM_CSC_MSA | FTM_CSC_ELSA;
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break;
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case 1:
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FTM1_MODE = FTM_MODE_WPDIS | FTM_MODE_FTMEN; // Disable write protection, Enable FTM1
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FTM1_SC = 0x00; // Set this to zero before changing the modulus
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FTM1_CNT = 0x0000; // Reset the count to zero
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FTM1_MOD = 0xFFFF; // max modulus = 65535
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FTM1_C0V = FTM1_TIMER_RATE / frequency; // Initial FTM Channel 0 compare value 65535
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FTM1_SC = (FTM_SC_CLKS(0b1) & FTM_SC_CLKS_MASK) | (FTM_SC_PS(FTM1_TIMER_PRESCALE_BITS) & FTM_SC_PS_MASK); // Bus clock 60MHz divided by prescaler 4
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FTM1_C0SC = FTM_CSC_CHIE | FTM_CSC_MSA | FTM_CSC_ELSA;
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break;
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}
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}
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void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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switch(timer_num) {
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case 0: NVIC_ENABLE_IRQ(IRQ_FTM0); break;
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case 1: NVIC_ENABLE_IRQ(IRQ_FTM1); break;
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}
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}
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void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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switch (timer_num) {
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case 0: NVIC_DISABLE_IRQ(IRQ_FTM0); break;
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case 1: NVIC_DISABLE_IRQ(IRQ_FTM1); break;
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}
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
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switch (timer_num) {
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case 0: return NVIC_IS_ENABLED(IRQ_FTM0);
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case 1: return NVIC_IS_ENABLED(IRQ_FTM1);
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}
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return false;
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}
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void HAL_timer_isr_prologue(const uint8_t timer_num) {
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switch(timer_num) {
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case 0:
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FTM0_CNT = 0x0000;
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FTM0_SC &= ~FTM_SC_TOF; // Clear FTM Overflow flag
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FTM0_C0SC &= ~FTM_CSC_CHF; // Clear FTM Channel Compare flag
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break;
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case 1:
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FTM1_CNT = 0x0000;
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FTM1_SC &= ~FTM_SC_TOF; // Clear FTM Overflow flag
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FTM1_C0SC &= ~FTM_CSC_CHF; // Clear FTM Channel Compare flag
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break;
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}
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}
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#endif // Teensy3.5 or Teensy3.6
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