finish layout

Signed-off-by: Thomas Schmid <tom@binary-kitchen.de>
This commit is contained in:
Thomas 2020-11-29 01:03:54 +01:00
parent 837f8a7699
commit 5f9f6fcd0c
11 changed files with 5649 additions and 87148 deletions

File diff suppressed because it is too large Load Diff

464
_autosave-poc_sfp_b2b.sch Normal file
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Wire Wire Line
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Wire Wire Line
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Connection ~ 3750 4150
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 4150 4150
Wire Wire Line
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Wire Wire Line
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Connection ~ 4250 4150
Wire Wire Line
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P 4950 3350
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F 1 "L" V 5049 3350 50 0000 C CNN
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Wire Wire Line
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F 2 "" H 5950 6950 50 0001 C CNN
F 3 "~" H 5950 6950 50 0001 C CNN
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0 1 1 0
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F 3 "~" H 5950 6750 50 0001 C CNN
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0 1 1 0
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F 2 "" H 5650 7550 50 0001 C CNN
F 3 "" H 5650 7550 50 0001 C CNN
1 5650 7550
1 0 0 -1
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Wire Wire Line
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Wire Wire Line
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Connection ~ 5650 6950
Wire Wire Line
5650 6950 5650 6750
Wire Wire Line
5850 7150 5650 7150
Connection ~ 5650 7150
Wire Wire Line
5650 7150 5650 6950
Wire Wire Line
5850 7350 5650 7350
Connection ~ 5650 7350
Wire Wire Line
5650 7350 5650 7150
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1 5650 3750
1 0 0 -1
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Connection ~ 5650 3350
Wire Wire Line
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Wire Wire Line
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Connection ~ 4750 4150
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P 6200 3550
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F 1 "LED" V 6148 3432 50 0000 R CNN
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F 3 "~" H 6200 3550 50 0001 C CNN
1 6200 3550
0 -1 -1 0
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1 6200 3900
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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1 1100 4800
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0 -1 -1 0
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349
_autosave-sfp_module.sch Normal file
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@ -0,0 +1,349 @@
EESchema Schematic File Version 4
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1 0 0 -1
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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1 6900 2750
1 0 0 1
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1 6600 2750
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$Comp
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AR Path="/5F49D702/5F43569F" Ref="R301" Part="1"
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1 6300 2750
1 0 0 1
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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3.3V
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GND
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RX+
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RX-
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TX+
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$Comp
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P 3800 2850
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AR Path="/5F4938C1/5F44119B" Ref="L201" Part="1"
AR Path="/5F49D702/5F44119B" Ref="L301" Part="1"
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F 3 "~" H 3800 2850 50 0001 C CNN
1 3800 2850
0 -1 -1 0
$EndComp
$Comp
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U 1 1 5F441779
P 2900 3150
AR Path="/5F43391E/5F441779" Ref="C?" Part="1"
AR Path="/5F4938C1/5F441779" Ref="C201" Part="1"
AR Path="/5F49D702/5F441779" Ref="C301" Part="1"
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F 3 "~" H 2900 3150 50 0001 C CNN
1 2900 3150
1 0 0 -1
$EndComp
$Comp
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U 1 1 5F441A92
P 3250 3150
AR Path="/5F43391E/5F441A92" Ref="C?" Part="1"
AR Path="/5F4938C1/5F441A92" Ref="C202" Part="1"
AR Path="/5F49D702/5F441A92" Ref="C302" Part="1"
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F 1 "100nF" H 3365 3105 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 3288 3000 50 0001 C CNN
F 3 "~" H 3250 3150 50 0001 C CNN
1 3250 3150
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 5F441F3E
P 4500 3850
AR Path="/5F43391E/5F441F3E" Ref="C?" Part="1"
AR Path="/5F4938C1/5F441F3E" Ref="C205" Part="1"
AR Path="/5F49D702/5F441F3E" Ref="C305" Part="1"
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F 1 "100nF" H 4615 3805 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 4538 3700 50 0001 C CNN
F 3 "~" H 4500 3850 50 0001 C CNN
1 4500 3850
1 0 0 -1
$EndComp
$Comp
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U 1 1 5F442435
P 4150 3850
AR Path="/5F43391E/5F442435" Ref="C?" Part="1"
AR Path="/5F4938C1/5F442435" Ref="C204" Part="1"
AR Path="/5F49D702/5F442435" Ref="C304" Part="1"
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F 3 "~" H 4150 3850 50 0001 C CNN
1 4150 3850
1 0 0 -1
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Wire Wire Line
2900 3000 2900 2850
Connection ~ 2900 2850
Wire Wire Line
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Wire Wire Line
3250 3000 3250 2850
Connection ~ 3250 2850
Wire Wire Line
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Wire Wire Line
3650 3600 3550 3600
Wire Wire Line
3550 3600 3550 2850
Connection ~ 3550 2850
Wire Wire Line
3550 2850 3650 2850
$Comp
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U 1 1 5F44F82D
P 4150 3100
AR Path="/5F43391E/5F44F82D" Ref="C?" Part="1"
AR Path="/5F4938C1/5F44F82D" Ref="C203" Part="1"
AR Path="/5F49D702/5F44F82D" Ref="C303" Part="1"
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F 1 "100nF" H 4265 3055 50 0000 L CNN
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F 3 "~" H 4150 3100 50 0001 C CNN
1 4150 3100
1 0 0 -1
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Wire Wire Line
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Text HLabel 2400 4100 0 50 Input ~ 0
GND
Wire Wire Line
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Wire Wire Line
2900 4100 3250 4100
Connection ~ 2900 4100
Wire Wire Line
3250 4100 4150 4100
Wire Wire Line
4150 4100 4150 4000
Connection ~ 3250 4100
Wire Wire Line
4150 4100 4500 4100
Wire Wire Line
4500 4100 4500 4000
Connection ~ 4150 4100
Text HLabel 4150 3250 3 50 Input ~ 0
GND
$Comp
L Device:L L?
U 1 1 5F44A49F
P 3800 3600
AR Path="/5F43391E/5F44A49F" Ref="L?" Part="1"
AR Path="/5F4938C1/5F44A49F" Ref="L202" Part="1"
AR Path="/5F49D702/5F44A49F" Ref="L302" Part="1"
F 0 "L302" V 3990 3600 50 0000 C CNN
F 1 "1uH" V 3899 3600 50 0000 C CNN
F 2 "Inductor_SMD:L_0805_2012Metric" H 3800 3600 50 0001 C CNN
F 3 "~" H 3800 3600 50 0001 C CNN
1 3800 3600
0 -1 -1 0
$EndComp
Wire Wire Line
3950 3600 4150 3600
Wire Wire Line
4150 3600 4150 3700
Wire Wire Line
4150 3600 4500 3600
Wire Wire Line
4500 3600 4500 3700
Connection ~ 4150 3600
Wire Wire Line
4150 2850 4700 2850
Connection ~ 4150 2850
Wire Wire Line
4500 3600 4700 3600
Connection ~ 4500 3600
Wire Wire Line
2900 3300 2900 4100
Wire Wire Line
3250 3300 3250 4100
Text HLabel 4700 2850 2 50 UnSpc ~ 0
VCC_T
Text HLabel 4700 3600 2 50 UnSpc ~ 0
VCC_R
Text HLabel 7700 2600 1 50 UnSpc ~ 0
VCC_R
Text HLabel 7600 2600 1 50 UnSpc ~ 0
VCC_T
Wire Wire Line
7600 2600 7600 2750
Wire Wire Line
7700 2600 7700 2750
Text HLabel 6600 2350 1 50 UnSpc ~ 0
VCC_T
Wire Wire Line
6600 2350 6600 2500
Text HLabel 8350 2550 1 50 UnSpc ~ 0
VCC_T
Wire Wire Line
8350 2550 8350 2600
Text HLabel 8350 4400 3 50 UnSpc ~ 0
VCC_T
Wire Wire Line
8350 4400 8350 4300
Wire Wire Line
7600 4250 7600 4450
Text HLabel 8650 3050 2 50 UnSpc ~ 0
RX_LOS
Text HLabel 8650 3850 2 50 UnSpc ~ 0
TX_FAULT
$EndSCHEMATC

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View File

@ -60,7 +60,7 @@
36,
37
],
"visible_layers": "7ffff_ffffffff"
"visible_layers": "007ffff_ffffffff"
},
"meta": {
"filename": "poc_sfp_b2b.kicad_prl",

View File

@ -240,7 +240,8 @@
"netlist": "",
"specctra_dsn": "",
"step": "",
"vmrl": ""
"vmrl": "",
"vrml": ""
},
"page_layout_descr_file": ""
},

View File

@ -1,29 +1,10 @@
update=22/05/2015 07:44:53
update=Sa 28 Nov 2020 23:40:15 CET
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -31,3 +12,244 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.2
TrackWidth3=0.25
TrackWidth4=0.5
TrackWidth5=0.7
TrackWidth6=1
TrackWidth7=1.3
TrackWidth8=1.6
TrackWidth9=2
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
ViaDiameter4=1
ViaDrill4=0.5
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
dPairWidth2=0.5
dPairGap2=0.25
dPairViaGap2=0
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25