2 Commits

Author	SHA1	Message	Date
etagle	0566badcef	Add memory barrier, optimal interrupt on-off ... Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)	2018-05-20 02:39:34 -05:00
Karl Andersson	428c54f2ad	[2.0.x] HAL for STM32F4 (#10434)	2018-04-17 17:33:29 -05:00