etagle
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0566badcef
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Add memory barrier, optimal interrupt on-off
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
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2018-05-20 02:39:34 -05:00 |
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Chris Pepper
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cc6d41e1d3
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Use a macro for HAL header redirection (#10380)
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2018-04-12 20:25:08 -05:00 |
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Scott Lahteine
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ac368f2788
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Add STEPPER_ISR_ENABLED() to HALs
Some also get a `HAL_timer_interrupt_enabled` function.
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2018-01-14 21:07:10 -06:00 |
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Scott Lahteine
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c2b1d51f16
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HAL whitespace and style cleanup
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2017-09-27 10:55:36 -05:00 |
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Scott Lahteine
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2af62a5d8d
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Apply spacing, const to some HAL code
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2017-08-31 18:33:07 -05:00 |
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teemuatlut
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f3e562e46e
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HAL for 32-bit Teensy (3.5, 3.6) architecture
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2017-08-31 18:15:07 -05:00 |
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