MPCNC/Firmware2
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f89f7c4a82
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157 Commits

Author SHA1 Message Date
Chris Pepper
f89f7c4a82 [2.0.x][LPC176x][Build] Force single precision constants, disable freestanding (#10892) 2018-05-28 19:38:22 -05:00
Scott Lahteine
9b9b62b218 delay(SERVO_DELAY) => safe_delay(servo_delay[servo_index]) 2018-05-28 03:44:32 -05:00
Bob-the-Kuhn
1c0ad8bbae wrong type of exit method 2018-05-26 08:17:03 -05:00
Bob Kuhn
235facd545 install AVRDUDE 5.10, faster disk find for LPC1768 (#10849) 2018-05-25 20:26:48 -05:00
Bob Kuhn
e2db509d58 [2.0.x] Update/Fix LPC1768 extra script upload_extra_script.py (#10843) 
* Use a different method to find the volume info in Windows
 2018-05-25 04:31:18 -05:00
Scott Lahteine
5f8591528e Remove #pragmas that don't help c files 2018-05-23 23:47:16 -05:00
Scott Lahteine
c89649b46e Suppress U8glib build warnings 2018-05-23 02:47:36 -05:00
Bob Kuhn
6dfbb39f83 [LPC1768] Add error-handling to upload script, update autobuild.py (#10802) 2018-05-20 21:22:04 -05:00
etagle
569df3fc0c Fix interrupt-based endstop detection 
- Also implemented real endstop reading on interrupt.
 2018-05-20 07:10:24 -05:00
etagle
0566badcef Add memory barrier, optimal interrupt on-off 
Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)
 2018-05-20 02:39:34 -05:00
Scott Lahteine
206014a957 Fix LPC176x timer functions 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-20 01:58:51 -05:00
Chris Pepper
9b64fdbc3a [LPC176x] HAL: Add missing program space definition (#10776) 2018-05-19 15:37:54 -05:00
Scott Lahteine
50270b53a0 Clear up some more compile warnings 2018-05-17 18:40:49 -05:00
etagle
40d7e12827 Removing warnings from compilation 2018-05-17 18:04:22 -05:00
Scott Lahteine
fb608938f8 Prevent compilation of unused u8g-oriented code 2018-05-14 13:31:04 -05:00
Scott Lahteine
37b15fe4cf Reorder HAL timer header items 2018-05-13 16:50:39 -05:00
Scott Lahteine
99ecdf59af Smarter MIN, MAX, ABS macros 
Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-13 04:52:56 -05:00
etagle
9d98a62699 Followup to HAL optimizations and delays 
- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.
 2018-05-13 00:46:23 -05:00
Scott Lahteine
a1062eec5b
Better handling of DELAY_NS and DELAY_US (#10716) 
Co-Authored-By: ejtagle <ejtagle@hotmail.com>
 2018-05-12 08:34:04 -05:00
Scott Lahteine
d1b619be52 Standardize some hexadecimals 2018-05-08 09:19:18 -05:00
Scott Lahteine
456cf971af HAL FastIO cleanup and fixes 2018-04-26 00:40:16 -05:00
Scott Lahteine
2578996631
[2.0.x] Emergency parser for multiple serial ports (#10524) 2018-04-25 20:58:00 -05:00
Chris Pepper
2242b98248 [LPC176x] Emergency Parser Feature (#10516) 2018-04-25 06:44:26 -05:00
Scott Lahteine
a3ce8a3fcd Add sanity checks for EMERGENCY_PARSER 2018-04-24 09:24:26 -05:00
Eduardo José Tagle
0c428a66d9 Proper AVR preemptive interrupt handling (#10496) 
Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.
 2018-04-23 22:05:07 -05:00
Scott Lahteine
29dda871cb Patch "upload_disk" to make python happy 2018-04-13 22:27:08 -05:00
Chris Pepper
cc6d41e1d3 Use a macro for HAL header redirection (#10380) 2018-04-12 20:25:08 -05:00
Bob-the-Kuhn
85014cd132 [2.0.x] LPC1768 - automatic selection of upload disk (#10374) 2018-04-11 14:41:16 -05:00
Bob-the-Kuhn
ab715c70d1 TMC SPI sanity-check and pins debugging (#10324) 2018-04-06 20:24:54 -05:00
Scott Lahteine
93305a2d5e Fix some spellings 2018-04-02 03:03:37 -05:00
Scott Lahteine
239902f861 Fix E2END and add EEPROM to Smart RAMPS 
Reference #9983
 2018-03-10 06:57:31 -06:00
Bob-the-Kuhn
3c58ca181c [2.0.x] Correct step pulse width on LPC1768, DUE & Teensy35_36 (#10016) 2018-03-09 02:11:28 -06:00
Scott Lahteine
98d48fc731 Followup to HAL_timer_restrain 
Followup to #9985
 2018-03-07 22:18:37 -06:00
Scott Lahteine
ca577c1638 Fix up various spacing, comments, and typos 2018-03-07 21:09:08 -06:00
Scott Lahteine
d45f19d385 Remove Unicode from var name 2018-03-07 19:08:44 -06:00
Chris Pepper
a1a88ebabc HAL function to ensure min stepper interrupt interval (#9985) 2018-03-07 17:53:25 -06:00
Scott Lahteine
beeed580b8
Implement digipots for MKS SBASE (#9927) 
Fix #9477
 2018-03-04 15:14:47 -06:00
Scott Lahteine
f3dbe19669 Tweaks to HAL codestyle 2018-02-25 04:38:17 -06:00
Scott Lahteine
90fa423737
Preliminary cleanup of #include structure (#9763) 2018-02-23 00:52:52 -06:00
Scott Lahteine
799e3b2b40 LPC1768 HAL formatting/comments 2018-02-22 14:36:17 -06:00
Scott Lahteine
a810e585db Drop HAL_timer_set_count 2018-02-20 03:10:39 -06:00
Scott Lahteine
ca55f2927a
Pulldown pin mode support (#9701) 
Implemented for LPC1768.
 2018-02-18 19:26:23 -06:00
Scott Lahteine
03d790451f
[2.0.x] HAL timer set/get count => set/get compare (#9581) 
To reduce confusion over the current timer count vs. the compare (aka "top") value. Caution: this re-uses the function name, changing its meaning.
 2018-02-10 20:42:00 -06:00
Scott Lahteine
b939a2e88c Watchdog conditional for LPC 2018-02-04 18:52:44 -06:00
Scott Lahteine
0891b58c30 #ifdef tweaks 2018-02-04 16:36:30 -06:00
Bob-the-Kuhn
3d72fe0730 snapshot 2018-02-03 21:28:05 -06:00
Scott Lahteine
33ec599ca0 Tweaky LPC1768 SPI spacing/style 2018-02-03 20:25:57 -06:00
Scott Lahteine
c46de340b7 Clean up trailing whitespace 2018-02-03 20:05:23 -06:00
Thomas Moore
e1fd9c08b3 [2.0.x] Add support for LPC1769 at 120 MHz (#9423) 2018-02-03 19:33:26 -06:00
Scott Lahteine
b13099de3f General cleanup of HAL code 2018-02-02 03:37:15 -06:00